I2C TRISE

[hazelnusse]

Posted on May 01, 2012 at 07:54

I would like to understand what the I2C TRISE register does.

The standard peripheral library effectively sets it to either:

I2Cx->TRISE = PCLK1 / 1000000 + 1;

or

I2Cx->TRISE = (PCLK1/1000000*300)/1000 + 1; 

For example, for a 36MHz peripheral 1 clock, PCLK1=36000000, this results in:

I2Cx->TRISE = 37;

or for fast mode:

I2Cx->TRISE = 11;

So, it seems like this can be interpreted as the number of peripheral cycles it takes for the SCL line to go rise. RM0008 mentions this as well:

The filter value can also be added to TRISE[5:0].

Does anybody know what this means exactly? I presume that this register somehow affects how many clock cycles the peripheral waits after releasing SCL to see if it has actually gone high (the slave could stretch the clock, so the master needs to verify the line has gone high after some period of time), but I really don't know. If this is the case, then it seems like you could use TRISE to cause the STM32 to wait a more or less than the I2C spec (300ns for fast, 1000ns for standard) before checking to see that the clock line has indeed gone high. If you knew your circuit had lower rise times, you could reduce TRISE to reduce some of the bus overhead; conversely, if you knew your bus had higher rise times, you could increase TRISE to make sure that SCL has time to go high. Has anybody experimented with this setting? Thanks, Luke #stm32-i2c-ccr #stm32-i2c

[waclawek.jan]

Posted on September 18, 2013 at 09:16

> If you refer to NXP I2C specifications, you will find that each mode must respect some timings.

> In the STM32F1/F2/F4/L1 I2C, these timings are hardware coded and depend on the value programmed in FREQ field. And what is the role of CCR field, then? JW

[lendre.sandrine]

Posted on September 18, 2013 at 15:23

CCR field is used to generate the SCL master clock.

FREQ is used by the hardware to generate data setup and hold times respecting the standards whatever APB frequency.

[waclawek.jan]

Posted on September 18, 2013 at 16:42

> CCR field is used to generate the SCL master clock.

> FREQ is used by the hardware to generate data setup and hold times respecting the standards whatever APB frequency.

Okay, but as FREQ is entered as the input clock/1MHz, it seems that the timing granularity is 1us. However, the most important clock-to-data timing is tSU;DAT, which is 250ns/100ns... How does this fit together? I also suspect, that FREQ is used to derive the start/stop timings (tHD;STA, tSU;STA, tSU;STO, tBUF), yet these are given in the standard mostly with 100ns granularity, too. Timing them with 1us granularity sounds quite inefficient. Can you please comment on this? --- Why couldn't *all* the timing be properly documented in the user manual? It takes only a well-described diagram, and a table, to do that; plus maybe some little text such as your explanation of TRISE above. I don't find anything ''difficult to explain'' in it, and the benifit is in satisfied users. Please mind, that your target audience are experienced engineers; and even if there surely are some amateurs around, they are bound to get educated, too... 😉 JW

[lendre.sandrine]

Posted on September 20, 2013 at 08:47

The timings granularity depends on the APB clock frequency.

FREQ is used only for data setup and hold times. CCR is used for all timings related to the master clock. If you refer to STM32F3 reference manual for instance, you will find a precise description of timings generation. The STM32F1 timings generation is quite similar except the fact you have less SW flexibility. The improvement of the reference manual based on this thread feedbacks are requested. Thanks and best regards Sandrine

[lendre.sandrine]

Posted on September 20, 2013 at 08:58

just precise my answer :

concerning data setup and hold times they are hardware coded in a loockup table depending on FREQ value.