2020-05-12 08:15 PM
// using Double-Buffer DMA
DMA_HandleTypeDef hdma ;
StreamBaseAddr = DMA_CalcBaseAndBitshift(&hdma) ; // get the stream base addr
if (HAL_DMAEx_MultiBufferStart_IT(&hdma, StreamBaseAddr, Buffer[0], Buffer[1], BUF_SIZE))
{
Error_Handler();
}
Is this function call, correct way to setup the MultibufferDMA? ..to find the base address of the source stream used?
How the interrupt for HalfCmpl & Cmpl handled?
Anyone used this DMA scheme?
Thanks.
2020-05-12 08:29 PM
How are you trying to use it? It's meant for transferring data from a peripheral, e.g. the ADC, to a double buffered memory. In this case, you would put "&ADCx->DR" as the source memory address. Not StreamBaseAddr.
TC interrupt is called when the transfer to the first buffer completes, then again when the transfer to the second buffer completes, and so on. HT interrupt is not enabled.
2020-05-12 10:39 PM
Thanks for the update. Here's what I wanted to do :
I want to use the DFSDM peripheral in multibufferDMA mode.
Currently it works ok in circular buffer mode (based on the STM's example use) but it's not what I want.
There are few HAL multibuffer driver function calls one of which as I mentioned above.
It needs the parameters : SourceAddr, Memory1Addr,Memory2Addr, DataLength.
For straight forward use, say for write to memory, the source is the Data register the DMA will read/write from the peripheral and the Destination is the Memory address.
For using this DFSDM block, which is the peripheral for the DMA, uses DMA2_Stream0 for it's DMA Xfers, hence I'm not sure what should be set as the Source Address for it's use.
Handling the HalfCmplt & Cmplt DMA interrupts, I have no problems as it's similar to other DMA modes.
Here's the code segment for what I thought of for setting up this DFSDM in multibuffer DMA mode :
// DFSDM_Filter MSP Initialization
extern uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) ;
extern DMA_HandleTypeDef hdma_dfsdm1_flt0;
extern int32_t Buffer[2][BUF_SIZE] ;
void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
{
uint32_t StreamBaseAddr ;
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(DFSDM1_Init == 0)
{
/* Peripheral clock enable */
HAL_RCC_DFSDM1_CLK_ENABLED++;
if(HAL_RCC_DFSDM1_CLK_ENABLED==1){
__HAL_RCC_DFSDM1_CLK_ENABLE();
}
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
/**DFSDM1 GPIO Configuration
PD3 ------> DFSDM1_CKOUT
PC3 ------> DFSDM1_DATIN1
*/
GPIO_InitStruct.Pin = DFSDM1_CLKOUT_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF3_DFSDM1;
HAL_GPIO_Init(DFSDM1_CLKOUT_GPIO_Port, &GPIO_InitStruct);
GPIO_InitStruct.Pin = DFSDM1_DATIN1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF3_DFSDM1;
HAL_GPIO_Init(DFSDM1_DATIN1_GPIO_Port, &GPIO_InitStruct);
}
/* DFSDM1 DMA Init */
/* DFSDM1_FLT0 Init */
if(hdfsdm_filter->Instance == DFSDM1_Filter0)
{
hdma_dfsdm1_flt0.Instance = DMA2_Stream0;
hdma_dfsdm1_flt0.Init.Channel = DMA_CHANNEL_8;
hdma_dfsdm1_flt0.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_dfsdm1_flt0.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_dfsdm1_flt0.Init.MemInc = DMA_MINC_ENABLE;
hdma_dfsdm1_flt0.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
hdma_dfsdm1_flt0.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
hdma_dfsdm1_flt0.Init.Mode = DMA_CIRCULAR;
hdma_dfsdm1_flt0.Init.Priority = DMA_PRIORITY_HIGH;
hdma_dfsdm1_flt0.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
// using Double-Buffer DMA mode
StreamBaseAddr = DMA_CalcBaseAndBitshift(&hdma_dfsdm1_flt0) ; // get the stream base addr
if (HAL_DMAEx_MultiBufferStart_IT(&hdma_dfsdm1_flt0, StreamBaseAddr, Buffer[0], Buffer[1], BUF_SIZE))
{
Error_Handler();
}
/* Several peripheral DMA handle pointers point to the same DMA handle.
Be aware that there is only one stream to perform all the requested DMAs. */
__HAL_LINKDMA(hdfsdm_filter,hdmaInj,hdma_dfsdm1_flt0);
__HAL_LINKDMA(hdfsdm_filter,hdmaReg,hdma_dfsdm1_flt0);
}
2020-05-12 10:54 PM
may be the data register of the DFSDM filter should be the Source address :