I like to access an adc ads8634 from TI via the spi bus. At fastest pace and with no or less interupts to use.

[LCE]

SPI -> DMA -> SRAM -> ?

That way you will only get DMA (half-) complete interrupts, how often depends on your buffer size.

Depending on what you want to do with the ADC data, I'd recommend an STM32 with DMA supporting double buffering.

[MOtto.1]

Hi, yes that is my intention. But my isues is i need to use the chip select for an input to the adc as a conversion start trigger. But when configureing the spi as a master format motorola and enable the NSS i need to enable and disable the spi to get NSS toggling.

  /* Disable all peripherals for now*/
  DMA2_Stream5->CR = 0;
  DMA2_Stream2->CR = 0;
  TIM1->CR1 = 0;
  SPI1->CR1 = 0;
  /* USER CODE END SysInit */
 
  /* Initialize all configured peripherals */
  MX_GPIO_Init();
  MX_USART2_UART_Init();
  MX_DMA_Init();
  MX_SPI1_Init();
  MX_TIM1_Init();
  /* USER CODE BEGIN 2 */
 
  /* DMA2 SPI1 receive */
  /* Setting source & target pointer for rx */
  LL_DMA_SetMemoryAddress(DMA2, LL_DMA_STREAM_2, (uint32_t)adc_data);
  LL_DMA_SetPeriphAddress(DMA2, LL_DMA_STREAM_2, (uint32_t)&SPI1->DR);
  LL_DMA_SetDataLength(DMA2, LL_DMA_STREAM_2, ADC_VALUE_COUNTS);
 
  DMA2_Stream2->FCR = 0;
 
  /* enable spi to do req on dma */
  LL_SPI_EnableDMAReq_RX(SPI1);
 
  /* DMA2 start now for rx*/
  LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_2);
 
  /* start SPI now */
  LL_SPI_Enable(SPI1);
 
  /* Setting source & target pointer for tx */
  LL_DMA_SetMemoryAddress(DMA2, LL_DMA_STREAM_5, (uint32_t)adc_channel);
  LL_DMA_SetPeriphAddress(DMA2, LL_DMA_STREAM_5, (uint32_t)&SPI1->DR);
  LL_DMA_SetDataLength(DMA2, LL_DMA_STREAM_5, ADC_CHANNEL_COUNTS);
 
  DMA2_Stream5->FCR = 0;
 
  temp = DMA2_Stream5->CR;
 
  /* DMA2 start now for tx*/
  LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_5);
 
  /* start TIM1 now and start update event*/
  LL_TIM_EnableDMAReq_UPDATE(TIM1);
  LL_TIM_EnableCounter(TIM1);

well this runs in an endless loop but with no control of the chip select. How could i have control of the NSS pin without using interrupts, because other wise i could do all in the interrupt.

Greetings

[Tesla DeLorean]

Then it's probably not going to work ideally.

For these types of things people typically add glue logic, in the form of a state-machine, or other combinatorial logic, in a CPLD, or something, to smooth the disparity in expectations, and can do so at wire rates.

[waclawek.jan]

Which STM32?

> How could i have control of the NSS pin without using interrupts

Using timers.

One way to pull this off is to generate both the framing and SPI SCK from two master-slave-coupled timers, and feed it back externally to SPI set as slave.

Sometimes this sort of protocols can be pulled off quite easily using the SAI module.

JW