I am working with an STM32F429 in a project and I am seeing random BusFaults, captured against erroneous execution of ldr r4, [r2, #12]. This is one example.
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‎2023-05-13 6:57 AM
I am working with an STM32F429 in a project and I am seeing random BusFaults in random code locations, very infrequently but obviously problematic. I traced one earlier to this instruction ldr r4, [r2, #12].
You'll see from the screen capture attached, R2 is 0x2000153d0, with offset #12 it should point to 0x200153e2. Looking at the memory view, the 32-bit data at location 0x200153e2 is 0xD0100000,
However at runtime the value in r4 is set to 0x90116bcc. which then subsequently cause lr to be incorrectly loaded, eventually throwing a bus fault at disassembly line 08041400.
All help greatly appreciated as I am scratching my head with this to the order of weeks.
I read something earlier about turning off caching?
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STM32F4 Series
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‎2023-05-13 8:13 AM
Check voltages and capacitors used for VCAP pins
Check flash wait states via operating voltage and speed.
Scope check the pointer before use
Is there an alignment flag enabled?
Up vote any posts that you find helpful, it shows what's working..
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‎2023-05-15 5:02 AM - edited ‎2023-11-20 5:33 AM
So far I have checked VCAPs and voltages.
I have these currently fitted https://spicat.kyocera-avx.com/product/mlcc/chartview/08053C225KAT2A.
And have now ordered some of these https://www.murata.com/en-eu/products/productdetail?partno=GCM21BR71E225KA73%23 which have much lower ESR.
The pin voltages are correct but I am seeing some reasonable spikes on the scope trace, so my thinking is that maybe it's this. Hoping the lower ESR capacitors will improve the situation.
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‎2023-05-15 6:09 AM
Your interpretation of above screenshot is probably incorrect and r4 got correctly calculated from lr.
What's at address 0xD010'0000, SDRAM?
It's then that SDRAM's content which is corrupted, so you should've checked that content, and then draw conclusions - e.g. is SDRAM's setup correct, does it refresh properly, isn't read timing off or too high coupling between tracks causing read data corruption, etc.;
JW
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‎2023-05-15 6:16 AM
Thanks JW, I had totally missed this, I will set the debugger going on this and check.
