How to use 2 gpio interrupts on same EXTI2 line

[SA.17]

Hi ,

I have connected switch to PC2 and PD2 (the are acting as gpio input),after trying to generate initial code using cubemx found that these two pins are on same gpio interrupt EXTI2 line , so cubemx is not allowing to have interrupt on both pins,is there anyway both can have gpio interrupts

[waclawek.jan]

> is there anyway both can have gpio interrupts

No.

[S.Ma]

This is something to check before making schematics.

[waclawek.jan]

If one of those pins has connectivity to a unused timer channel, that can be used as an external interrupt too.

Also, using interrupts to handle switches is often overrated, and usually they can be more effectively polled in any regular process.

JW

[Bob S]

> Also, using interrupts to handle switches is often overrated, and usually they can be more effectively polled in any regular process.

This --^

Unless your switches are debounced by external circuitry, you most likely will get several interrupts on each press and release. If you are trying to have the switch interrupt wake up the CPU, then do that, but then debounce the switch press in software. But you are still limited to one pin into an EXT interrupt unless as @Community member​ suggested you can run one of the switches to a timer.

[Piranha]

The thing, that surprises me, is the fact that for H7 series ST changed/redesigned peripherals so much, but EXTI was left the same very limited one. Doesn't they understand that there should be an "interrupt per port", not this in-flexible "interrupt per pin number(s)"?

For debouncing I use a combination of interrupt and software timer. But it should be noted that proper hardware debounce works very good also without software debounce. For proper hardware debounce example look at USER button on STM32F769I-DISCO board. And for wrong and stupid example how to NOT do this look at USER button on NUCLEO-144 boards.

[turboscrew]

Read the pin levels in interrupt. They work as GPIO inputs too.

If you use CubeMX, there is a place for user code in the ISRs.