How to set up the adc sampling time.

[GHARI.1]

Hi,

I am using ADC of STM32H743ZI which is configured as 16 bit, ADC clock =36.5MHz,Tsampling=1.5cycles in continuous conversion mode . I am using DMA technique to collect the data using a buffer size of 4096 in circular mode.

The input is sine wave of peak to peak voltage =3.3V whose frequency varies from 1Hz to 20K Hz.

In debug mode when I observed data stored in buffer I am able reconstruct the signal back but accuracy is very less (sample to sample there is lot of voltage difference) for high frequencies.

Since Tsampling is 1.5cycles and Tconversion is 8.5Cycles and ADC clock is 36.5 MHz sampling speed would be 3.65Msamples/sec.

What might be the issue for this low accuracy whether DMA is not able to store this high sampling speed data or Tsamping is creating a problem. Can any one help me out solving this problem.

[GHARI.1]

Hi @QSHAO.1​ can you say me why you have considered sampling time as 42ns is 11 time constants is 7.8ns with R=170 and c=4pf

[QSHAO.1]

1.5x(1/36.5MHz)= 42nS, the 42nS is sampling time from 1.5 cycle and 36.5MHz ADC clock you mentioned above.

[GHARI.1]

so that is the minimum possible sampling time I am giving input as sine wave using function generator directly to PA0 which is direct channel do I need to use a buffer to drive ADC or not needed.

[QSHAO.1]

the function generator is with enough drive capability, so no buffer needed I think.

[GHARI.1]

Ok right now I am using Timer to trigger adc at 100KHz sampling frequency and the input is sine of 1KHz I am not using DMA instead I am using array to store the data but the data I obtained is not so accurate,.

[GHARI.1]

Here adc continuous conversion mode is enabled to disabled.

[TDK]

> In debug mode when I observed data stored in buffer I am able reconstruct the signal back but accuracy is very less (sample to sample there is lot of voltage difference) for high frequencies.

If you're getting data back that looks like the expected signal, but with noise, there is no problem with DMA or the code.

Noise can come from many sources. At 3+ Msps, you're going to have to deal with some of it.

How much noise are you seeing? Can you show a plot of the original and the reconstructed signal?

Is this a custom board? Is the VREF+ line stable and does it have sufficient capacitance?

[GHARI.1]

I am using Nucleo-H743ZI2 standard board. I have plotted the data using usart communication with 250K baud rate which is very less compared to sampling speed so this is not accurate.

I am able to say that reconstruction is happening by observing the data in buffer by seeing its variation in debug mode.

[GHARI.1]

For high input frequencies like10kHz the data in buffer after converting to voltage it is varying as (0V-1V-2V-3V-2V-1V-0V) there is lot of variation in voltage. May be it is taking less no of samples?