How to Reset STM32 Timer Internal Trigger Connections

[JAitc.1]

I'm using the STM32H735 to create a sequence of PWM signals. I have timers TIM1, TIM2, TIM4, and TIM24 all connected in a slave timer chain. TIM1 triggers TIM2 with ITR0. TIM2 triggers TIM4 with ITR1, and TIM4 triggers TIM24 with ITR3. Each link in the trigger chain is done with a timer channel in "Output Compare no Output" mode setup as the TRGO event.  These are the slave modes in the chain:

TIM1: disable

TIM2:  Trigger Mode (ITR0)

TIM4:  Trigger Mode (ITR1)

TIM24:  Trigger Mode (ITR3)

This all works perfectly but only the first time. If I stop all 4 timers and try to restart the sequence, only the PWM output from TIM1 starts again. The PWM output from TIM2, TIM4 and TIM24 fails to start. 

Here is some pseudo code to show what I have.

The sequence is started with:

// TIMER 24

HAL_TIM_Base_Start(&htim24);

HAL_TIM_PWM_Start(&htim24, TIM_CHANNEL_4);

// TIMER 4

HAL_TIM_Base_Start(&htim4);

HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3);

HAL_TIM_OC_Start(&htim4, TIM_CHANNEL_2);

// TIMER 2

HAL_TIM_Base_Start(&htim2);

HAL_TIM_OC_Start(&htim2, TIM_CHANNEL_3);

HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4);

// TIMER 1

HAL_TIM_Base_Start(&htim1);

HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1);

HAL_TIM_OC_Start(&htim1, TIM_CHANNEL_2);

The sequence is then stopped with:

// TIMER 1

HAL_TIM_Base_Stop(&htim1);

HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_1);

HAL_TIM_OC_Stop(&htim1, TIM_CHANNEL_2);

// TIMER 2

HAL_TIM_Base_Stop(&htim2);

HAL_TIM_OC_Stop(&htim2, TIM_CHANNEL_3);

HAL_TIM_PWM_Stop(&htim2, TIM_CHANNEL_4);

// TIMER 4

HAL_TIM_Base_Stop(&htim4);

HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3);

HAL_TIM_OC_Stop(&htim4, TIM_CHANNEL_2);

// TIMER 24

HAL_TIM_Base_Stop(&htim24);

HAL_TIM_PWM_Stop(&htim24, TIM_CHANNEL_4);

After the stop code the all 4 PWM signals stop. When the start code is run again, only TIM1_CH1 has PWM output. I suspect there needs to be a manual reset of the Internal Trigger connections for TIM2, TIM4 and TIM24 but I don't see anything for this in the HAL. Does anyone know what's required to reset the timers in this situation? Thanks in advance.

[JAitc.1]

Just to clarify: When I say "only the first time" I mean, when timer start code is run the first time, all 4 PWM outputs keep running correctly until the timer stop code is run. The problem occurs when the timer start code is then run a second time.

[ypkdani]

Hello,

did you find a solution? i have the same problem

[waclawek.jan]

Read out the timers' registers, first in working, then in non-working state, and check/compare/post.

JW

[aasil]

i have same problem when stop pwm and start again slave timer has 100% Duty cycle, do you find a solution?

[Cruvix]

Hello !

I had the same problem when I want to generate two PWM signals shifted by an adjustable delay. I found the answer in this part of the reference manual of the STM32H723/733, STM32H725/735 "43.3.10 Output compare mode". In this part, I have seen :

"The output pin can keep its level (OCXM=0000), be set active (OCxM=0001), be set inactive (OCxM=0010) or can toggle (OCxM=0011) on match."

In my project, made with CubeMX, I have set up "active level on match", but it must be "toggle on match" (TIM_OCMODE_TOGGLE in code for sConfigOC.OCMode).

My hypothesis is that on the first capture of the OC2REF for the slave timer, the output pin stays always high so when we restart the timer we cannot trigger, because the signal is high. I'm not sure if it is the correct understanding, but it works for me :)

Regards.