How to configure OctoSPI in Quad mode with PSRAM for memory mapped write access? Getting Hard Fault (FORCED, IMPRECISSERR) when write is attempted.

[Fero]

Hi there,

I trying to configure octospi on STM32H7A3 to work with LY68L6400 PSRAM via quadspi.

I have followed AN505 and managed to init, write and read from the memory successfully in indirect mode.

Now I am trying to map the PSRAM to memory. I can read from it, but when I attempt to write to the memory I get the Hard Fault (FORCED, IMPRECISSERR).

void PSRAM_Init()
{
	OSPI_RegularCmdTypeDef cmd;
 
	//switch to qspi mode
	cmd.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
	cmd.FlashId = HAL_OSPI_FLASH_ID_1;
	cmd.DummyCycles = 0;
	cmd.DQSMode = HAL_OSPI_DQS_DISABLE;
	cmd.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
 
	cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
	cmd.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS;
	cmd.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
	cmd.Instruction = 0x35;
 
	cmd.AddressMode = HAL_OSPI_ADDRESS_NONE;
	cmd.DataMode = HAL_OSPI_DATA_NONE;
	cmd.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
 
	ASSERT(HAL_OSPI_Command(&hospi1, &cmd, 100) == HAL_OK);
 
	//indirect write
	char str[] = " *** Hello world *** ";
 
	cmd.OperationType = HAL_OSPI_OPTYPE_COMMON_CFG;
	cmd.FlashId = HAL_OSPI_FLASH_ID_1;
	cmd.DummyCycles = 0;
	cmd.DQSMode = HAL_OSPI_DQS_DISABLE;
	cmd.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
 
	cmd.InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES;
	cmd.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS;
	cmd.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
	cmd.Instruction = 0x38;
 
	cmd.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
	cmd.AddressSize = HAL_OSPI_ADDRESS_24_BITS;
	cmd.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
	cmd.Address = 0;
	cmd.NbData = sizeof(str);
 
	cmd.DataMode = HAL_OSPI_DATA_4_LINES;
	cmd.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
 
	cmd.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
 
	ASSERT(HAL_OSPI_Command(&hospi1, &cmd, 100) == HAL_OK);
	ASSERT(HAL_OSPI_Transmit(&hospi1, str, 100) == HAL_OK);
 
	//set read configuration
	cmd.OperationType = HAL_OSPI_OPTYPE_READ_CFG;
	cmd.FlashId = HAL_OSPI_FLASH_ID_1;
	cmd.DummyCycles = 6;
	cmd.DQSMode = HAL_OSPI_DQS_DISABLE;
	cmd.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
 
	cmd.InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES;
	cmd.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS;
	cmd.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
	cmd.Instruction = 0xEB;
 
	cmd.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
	cmd.AddressSize = HAL_OSPI_ADDRESS_24_BITS;
	cmd.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
	cmd.Address = 0;
	cmd.NbData = 1;
 
	cmd.DataMode = HAL_OSPI_DATA_4_LINES;
	cmd.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
 
	cmd.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
 
	ASSERT(HAL_OSPI_Command(&hospi1, &cmd, 100) == HAL_OK);
 
	//Set write configuration
	cmd.OperationType = HAL_OSPI_OPTYPE_WRITE_CFG;
	cmd.FlashId = HAL_OSPI_FLASH_ID_1;
	cmd.DummyCycles = 0;
	cmd.DQSMode = HAL_OSPI_DQS_DISABLE;
	cmd.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
 
	cmd.InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES;
	cmd.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS;
	cmd.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
	cmd.Instruction = 0x38;
 
	cmd.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
	cmd.AddressSize = HAL_OSPI_ADDRESS_24_BITS;
	cmd.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
	cmd.Address = 0;
	cmd.NbData = 1;
 
	cmd.DataMode = HAL_OSPI_DATA_4_LINES;
	cmd.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
 
	cmd.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
 
	ASSERT(HAL_OSPI_Command(&hospi1, &cmd, 100) == HAL_OK);
 
	//map to memory
	OSPI_MemoryMappedTypeDef cfg;
	cfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE;
	cfg.TimeOutPeriod = 10;
 
	ASSERT(HAL_OSPI_MemoryMapped(&hospi1, &cfg) == HAL_OK);
 
	uint8_t * psram = (uint8_t *)0x90000000;
 
	DBG("PSRAM test '%s'", psram); //Print out PSRAM test ' *** Hello world *** '
 
	*psram = '@'; //HARD FAULT!!!!
 
	DBG("PSRAM test '%s'", psram);
 
	while(1);
}

Reading is working fine, checked with logic analyse.

The write to the PSRAM is not attempted, no communication on the external bus.

What am I doing wrong?

[Samuel4]

Hi

Do you have any news on this? I have run into the same problem. Read access works fine, however, writing throws the same hardfault.

[Fero]

I have it working now thanks to ST support:

There is an errata for this, enable DQS during write operation in memory mapped mode

cmd.DQSMode = HAL_OSPI_DQS_ENABLE;

The DQS should be enabled in memory mapped mode during write operations (DQSE

in OCTOSPI_WCCR set) regardless of the GPIO Pin configuration.

If DQS pin is not needed by the memory, the application can use the DQS pin for

other usages without impacting the workaround.

Beware, OSPI interface is connected to AXIM bus which is 64-bit.

If you need byte access, set this area as strongly-ordered by MPU.

You can find more info in AN4838

[Samuel4]

Thank you! It works now.