How memory-mapped works on STM32L4?

[djunho]

Hello all,

I am trying to implement an external loader for my board. Which uses a W25M02GV (QSPI NAND FLASH)

I am following the https://github.com/STMicroelectronics/stm32-external-loader

I am trying to configure an STM32L4 to use this memory in mapped-mode, but I didn't understand how memory-mapped works for the underground. At least I didn't found any doc that explains it.

As I am understanding from its datasheet, this memory doesn't have any read command with the page address that outputs the content.

It seems necessary to use 2 commands: The first one (13h) receives the page address and then gets the page content in an internal buffer. Then afterward, a second command reads it from this buffer (there are a continuous mode, which at the end of the buffer continue from the next page and so on)

But, it seems that when configuring the memory-mapped mode it needs a single read command with a page address to work?

Thanks =)

[OOni]

Hello see Application Note AN5050 Octo-SPI interface on STM32 microcontrollers

[Andreas Bolsch · Accepted solution]

Simply put: The QSPI/OctoSPI-Interface is designed for NOR flash, where a single command allows access to an arbitrary memory location. NAND flash don't support this as you already found out yourself. Even if there would be such a command: NAND flash don't use linear address space, but page oriented where the page size is not necessesarily a power of 2. Hence there would be gaps between the pages. And even if not: Handling of bad pages causes another sort of gaps. So, no useful way to use NAND flash in memory mapped mode (at least, if you're going to access the entire memory). Only indirect mode is possible.

[djunho]

Thanks for your reply!

This info is not on the manual of MCU. At least not so directly.

From the manual (RM0432 Rev 7) I got this:

The OCTOSPI supports most external serial memories such as serial PSRAMs, serial
NAND and serial NOR Flash memories, HyperRAM™ and HyperFlash™ memories, with
the following functional modes
• Indirect mode: all the operations are performed using the OCTOSPI registers.
• Status polling-mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting.
• Memory-mapped mode: the external memory is memory mapped and it is seen by the
system as if it was an internal memory, supporting both read and write operations.

As you can see, it is not clear that memory-mapped doesn't work with NAND memories.

And, as I've never worked with NOR flash, I didn't know this difference. Thanks again for explaining =)

[Tesla DeLorean]

Have you worked with NAND? Not exactly byte addressable is it? Or random access at anything smaller than block size.

Not ST's job to cover the functionality or appropriateness of any given device you might want to attach.

It could probably "map" the memory, and issue commands based on those accesses, this functionality would probably be less than ideal, and need to be done with extreme care so the FIFO's don't get confused.

[djunho]

I understand your point. They can't provide functionality that works with every device. I agree.

This is why my question was how memory-mapped works.

With this info, I would have noticed earlier that it did not fit in my case of use =)

Or even trying to adapt my case to it.

[pkoevesdi]

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@djunho wrote:

With this info, I would have noticed earlier that it did not fit in my case of use =)

Or even trying to adapt my case to it.

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I agee, not supporting something is one thing and totally understandable. But to claim the opposite in the reference manual is misleading and costs time.

So, I'd suggest to make a change to the reference manual(s) at this point.

I had several occasions, where the STM manuals could not keep up with the quality of the product. But the documentation is an essential part of the product and has a large share of the overall value.