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How do I identify Brown out reset (BOR) condition from embedded software?

CDesh
Associate III

I would like to distinguish POR/PDR and BOR condition. Let me know if there is a way to identify this from embedded software for stm32l072cz.

1 ACCEPTED SOLUTION

Accepted Solutions
Amel NASRI
ST Employee

Hi @CDesh​ & @KnarfB​ ,

Comparing both reference manuals of both STM32L4 and STM32L0 and precisely RCC_CSR register, I noted that bit 27 is described as following:

  • STM32L4
    • Bit 27 BORRSTF: BOR flag. Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit.
      • 0: No BOR occurred
      • 1: BOR occurred
  • STM32L0
    • Bit 27 PORRSTF: POR/PDR reset flag. This bit is set by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit.
      • 0: No POR/PDR reset occurred
      • 1: POR/PDR reset occurred

So either for L4 or L0, the flag is the same and it is set when a power reset occurs.

In STM32L0, BOR is not available on all devices.

So for both STM32L0 & STM32L4, we can identify POR/PDR/BOR condition based on the bit 27 of RCC_CSR register.

Hope my answer helped you, when your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

-Amel

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

View solution in original post

6 REPLIES 6
KnarfB
Principal III

Evaluate the __HAL_RCC_GET_FLAG(RCC_FLAG_BORRST) flag and related reset causes at the very beginning of main. Use __HAL_RCC_CLEAR_RESET_FLAGS() to clear the flags after evaluation.

hth

KnarfB

CDesh
Associate III

Thanks for your quick response.

I do not see RCC_FLAG_BORRST flag availability in stm32l0cz MCU. Is there a way to include this flag to my MCU which is available in stm32l4xx.

Ooh, you're right. That's different from other families. No idea, sorry. Maybe it cannot be distinguished from a POR?

Amel NASRI
ST Employee

Hi @CDesh​ & @KnarfB​ ,

Comparing both reference manuals of both STM32L4 and STM32L0 and precisely RCC_CSR register, I noted that bit 27 is described as following:

  • STM32L4
    • Bit 27 BORRSTF: BOR flag. Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit.
      • 0: No BOR occurred
      • 1: BOR occurred
  • STM32L0
    • Bit 27 PORRSTF: POR/PDR reset flag. This bit is set by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit.
      • 0: No POR/PDR reset occurred
      • 1: POR/PDR reset occurred

So either for L4 or L0, the flag is the same and it is set when a power reset occurs.

In STM32L0, BOR is not available on all devices.

So for both STM32L0 & STM32L4, we can identify POR/PDR/BOR condition based on the bit 27 of RCC_CSR register.

Hope my answer helped you, when your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

-Amel

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

CDesh
Associate III

@Amel NASRI​  Thanks for your response.

Is it by part number of STM32L0, where I can identify if BOR is available or not?

If BOR is available, once again how do identify it be different from POR/PDR?

is BOR enabled by default on STM32L0 (where BOR is available)?

Hi @CDesh​ ,

BOR is not available for devices operating from 1.65 to 3.6 V and the power supply is monitored by the POR/PDR in this case.

For devices operating from 1.8 to 3.6 V, the BOR is always active and unless disabled by option byte it will mask the POR/PDR threshold.

This means that the POR and PDR are used only when the BOR is disabled.

All these details are available in the reference manual RM0367. Have a look to the section 6.2 Power supply supervisor for some more details.

-Amel

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.