How can STM32 ADC detect higher voltage than actual - internal temperature sensor testing

[krzysztof-idb]

Hello

When adding the internal temperature sensor reading in the STM32H750 micro FW, out of curiosity I collected voltage reading data based on different sampling times.

Based on our ADC clock speed (37.5 MHz) and the datasheet requirements for the temperature sensor (minimum sampling time 9 us) I calculated that the minimum cycles required for the ADC sampling are 337.5.

This works out well and with the sufficient sampling time provided I obtain appropriate temperature reading of 27C.

Now it seems understandable that when not enough sampling time is provided, the internal ADC SAR capacitors do not have enough time to charge and in result the input voltage conversion is lower than actual.

However, I am curious about the result for the cycle time 64.5, where the resulting voltage is slightly greater than actual (all the results are consistent i.e. I can run the same FW in a loop and always roughly the same counts are detected).

Looking at the ADC description in AN2834 section 2.1, we can see that the final SAR result depends on a number of comparations and the position and number of capacitors used in each approximation step will depend on the input voltage and previous step results.

Is it simply due to chance that in this case the voltage reading is higher than expected but it could be either way since any of the capacitors may not have charged as expected? How could the ADC error be related to the lower bits (smaller charge capacitors) if they should in theory charge faster than the largest required cap to detect ~600 mV?

[STOne-32]

Dear @krzysztof-idb ,

Thanks for the interesting observation and also confirming that minimum sampling time is inline with our requirements of 9us 🙂 .  
As in the experiment above we are out of specification of the product and features, It will be just guesses , in general such Temperature sensor ( Analog) is a kind of « source current » implementation at design side with comparators to a reference voltage which is also a « source of current » that is calibrated across all Voltages, Temperatures etc. The settling time of this source will transit by different modes of charging and stabilisation and may ring until we reach the 9us ( which is guaranteed by design across all conditions) . So the value read which is above the nominal one may reflect a reading while the source is not yet stabilized enough ,   Then comes the ADC SAR architecture  and sampling caps .

This is my guesses .  You can play further with the ADC frequency to tune more the results and observations.
ciao

STOne-32

[BarryWhit]

I have only a rudimentary understanding of how SAR ADCs work, but if I understand you and them correctly - you are assuming that the approximation value should approach the sampled voltage monotonically - and that assumption is not valid.

The WP article on SAR ADCs suggests the helpful mental model of the SAR process as binary search.

In line with that, what you should see at every step is only that the absolute value of the error, between the approximation and the sampled value monotonically decreases (or to be pedantic, non-increases) with each step.

And in fact, in your example, it does:

Cycle time	Approx mV.	|622mv-approx|
1.5	135	487
2.5	150	472
8.5	234	388
16.5	341	281
32.5	557	65
64.5	638	16
387.5	622	0
810.5	622	0

As another example, this animation from WP  shows that, depending on the sampled value, there can be some "overshoot" during some intermediate step(s), just like in your example.

https://en.wikipedia.org/wiki/File:4-bit_Successive_Approximation_DAC.gif

[AScha.3]

Hi,

maybe, i can give you some idea ...

1. your experiment is out of "defined working area" , as @STOne-32  explained .

2. The ADC is a charge redistribution SAR ADC , read a little, how this works, if you want:

https://www.renesas.com/us/en/document/apn/r14an0001-operation-sar-adc-based-charge-redistribution-rev100?language=en

or from STM

https://www.st.com/resource/en/application_note/an2834-how-to-optimize-the-adc-accuracy-in-the-stm32-mcus-stmicroelectronics.pdf

3. Such ADC has an input sample-hold cap, maybe 5pF , that has to be charged to the input voltage it should get.

So needs some minimum time, depending on the source impedance also.

Now you know, why its working fine, if you keep to this (calculated) values for sampling time vs. source impedance.

4. But there is a small "black hole" in this story - nobody talks about:

after the SAR conversion, switching its internal caps...until sequence finished, the "input sampling cap" still has some charge, depending on the sequence/hardware inside the ADC structure.

THIS charge will come OUT of the ADC, when the next ADC sequence starts with switching the cap to the input pin.

And so you get a small current coming out from the ADC input, that depends at first on the speed of conversions, the basic internal structure of the ADC and (maybe) on the last voltage level, the sampling cap was charged on the previous conversion.

This "current" can easily be measured and might in some "border cases" give strange phenomena - as here, when you see a "magic" voltage increase at some certain high-impedance input and certain sampling time and speed.

So you know now...why this can happen. 🙂

btw 

Some ADC's dont show this side effect, here the sampling cap is discharged to a fixed voltage, (most time GND, 0V) so you get no such magic effect - but this needs a extra step in the sequence, making the ADC one clock slower. So most ADC have the built-in magic , because they want them to be as fast as possible.