I'm trying to see what's possible in terms of a bootloader in a custom application of an stm32f722.
We have an external 2-megabyte flash chip on the QSPI bus, along with the internal 512-kilobyte flash. I'd like to make the bootloader stored on internal flash as tiny as possible; the best way to do this is to make it evaluate the image stored on internal flash as well as external, and simply jump to whichever one passes this evaluation. I'd then put the code to handle USB DFU mode, SPI download mode, UART download mode, etc., all on the external flash, and run it from there only if needed.
This requires being able to write that code into the external flash using SWD (further upgrades can be done over any of the protocols above, but for the first time we need to use SWD as the code isn't on the device yet to do the other protocols). What I can't tell is whether the SWD implementation on this chip allows writes to flash chips mapped on the external QSPI bus -- does the MEM-AP port (which I assume exists, because it's possible to update the internal flash over SWD) cover the registers used to configure QSPI? Does it cover the 0x80000000 - 0x9fffffff memory range that maps to the QSPI bus?
Is the set of SWD ports that the stm32f722 has, documented anywhere? I could not find it in either the datasheet or the reference manual (RM0431). I've read the "ARM Debug Interface v5 Architecture Specification" doc from ARM, but that only explains how the protocol works and what the ports need to look like, not how they're implemented. I also don't see any app notes about this -- the closest one is AN4989, the "debug toolbox", but it doesn't seem to cover the available ports, only how to mess with the core's execution.
Thanks for any information!
