How can represent logical gates in software of STM32F429I?

[AAbed.1]

Hi All;

I am working on an STM32F429I timer (PWM-mode1) to obtain two signals then I want to use AND gate inside the program (the input is the two signals come from timer Ch1 &Ch2) and designate one pin to be the final output.

[S.Ma]

If you use the same timer for the compare toggles, you will be guaranteed synchronized generation.

[AAbed.1]

is that ok

HAL_GPIO_WritePin(GPIOG,GPIO_PIN_9, ( HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_5) && HAL_GPIO_ReadPin(GPIOC, GPIO_PIN_8))? GPIO_PIN_SET : GPIO_PIN_RESET);

[AAbed.1]

I want to design the following signal ---->>>>

[AAbed.1]

I want to design the following signal--->>>

[TDK]

Assuming your waveform is periodic, it's equivalent to starting the first pulse at t=0 and the second pulse at T=T/2. I'm sure you could manage that with two synchronized timers. Not sure about two channel within the same timer.

You could even keep the centers at 0.25T and 0.75T using center-aligned mode.

[henry.dick]

yes.

[AAbed.1]

Do you have example about that

Thanks