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Hardware oversampling on ADC1 & 2 on H743VIT6

Senior III

I'm trying to optimize the H743's hardware oversampling on ADC1 & 2 at 384KHz sampling rate, it reduces the noise but I'd like some advice on the settings.

The H743 ref. manual state that the oversampling Ratio values are 0 - 1023, setting the number of additional oversamples, per sample, 0 = none, 1 = 1 extra sample (2 samples taken).

Of course as the averaging is done by shifting, only power of 2 values would work:-

2x(Ratio=1),4x(R=3),8x(R=7),16x(R=15),32x(..),64,128,256,512,1024,2048 which then requires -> ADC_RIGHTBITSHIFT_1, ..., ADC_RIGHTBITSHIFT_11.

RightBitShift is the shift (division) required for averaging, binary, so stepping in power2, 1=div2, 2=div4, etc, 11 values allowed, so max. us 2^11 = 2048, in this case 1024 samples per sample!

So Ratio cannot be any value from 1-1023, but only 1, 3, 7, 15, etc. Is that correct?

Another consideration not covered in the STM manuals is the ADC clock frequency required for oversampling to work.  Clearly, the hardware oversampler needs to have both the time and clock rate needed, so as I am using the fastest sampling time I've set the new ADC divider on the H743 to 1, it was 2.  So it can do one extra sample maximum.

Would that be correct or have I missed something?