HAL SPI RX function problem: long delay between two cycles of SCK during HAL_SPI_Receive() execution

[RGalvez]

Hi all!

I've found some strange issues during my reception of data at SPI interface using HAL functions.

The problem is that between each two complete cycles (8 periods) of SCK signal, the SCK line stays idle without reading any data. With longer streams of data, the acumm delay is bigger so it's a problem. In my application, the SPI TX/RX is critical and execution task time must be as short as possible.

if (hspi1.State == HAL_SPI_STATE_READY) {
      HAL_SPI_Transmit(SPI1_DataLink.SPI_Handler, (uint8_t*)localB->buff, localB->DataTypeConversion1,
    		  SPI1_DataLink.timeOut);
      HAL_SPI_Receive(SPI1_DataLink.SPI_Handler, (uint8_t*)G_SPI1_DataBufferRx, SPI1_DataLink.nb2Rcv, SPI1_DataLink.timeOut);
    }

 D4-->SCK D3-->MISO D2-->MOSI D1-->Chip Select

As you can see inter 2-byte space is 2.82us while SCK clock is 120ns period, Im wasting too much time.

Ive read that is a known issue that can be accomplished forgetting HAL libraries use and going into low-level register functions.

But for easier implementation, I would like to solve the problem with HAL libraries if possible due to I've implemented all my code using HAL functions.

There is another stranger issue... when I just transmit with HAL_SPI_Transmit() function these delays completely dissapear.

D5-->GPIO measuring HAL function execution time

In a future post I will ask about why Im losing 2.5us between start of HAL_SPI_Transmit() execution and first SCK cycle or 5.54us between last SCK and end of mentioned function execution...

[waclawek.jan]

Which STM32?

Cube/HAL is not written for best timing. Easier coding means sloppy result. Choose your preferences.

Try switching on compiler optimization.

JW

[RGalvez]

I'm working with the F303.

Yes, I'm going down into register level but as it is a known issue (from a couple years ago), maybe someone has found the solution remaining at HAL level

After compiling my receiving function with __attribute__((optimize("-Ofast"))) inter-SCK space lows from 2.82us to 2.70us.

[Gumer RoMa]

Could you solve this issue? I'm facing the same problem.

[S.Ma]

SPI is high bit rate and deserves DMA block transfer. SPI should be using Transmit receive function, so 2 DMA channels : RX and TX to 2 buffer of same size. If master, DMA TX set the number of SCK clocks while transaction ends by receive dma block interrupt.