2022-03-24 12:24 PM
Bus speed - 100kbit/s in CAN 2.0 mode
FDCAN clk - 48Mhz
Prescaler - 24 (bit length 20tq)
TQ1 - 15 (sample point 80%)
TQ2 - 4
SJW - 4
Receiving CAN messages without any problems, bus seems to be ok, even if FDCAN in normal mode(error counters are 0). But if I try to send something, bus nodes put Error state after the transmitted frame. Tried to adjust the sample point from 50% to 90% - the same. Tried to use HSE as clock source (12Mhz) instead of PLL1 - no differences. Tranceivers are TJA1041, that work perfectly on Cortex - M4 MCU with the same bus. I noticed 1 us difference between recessive bit of the transmitted frame and any of received frames (~9.6us against ~10.5us), but slight speed adjustment leads to receive errors.
2022-03-25 02:00 AM
Hello,
I think you wanted to say 100kbit/s
Try to decrease the prescaler as much as possible and increase TQ1 and TQ2 and use HSE+PLL as source clock to match 100kb/s.
I don't know what is your system clock value but please try to use higher frequencies.
2022-03-25 09:04 AM
Sure, I ment 100kb/s.
HSE - 12Mhz
Tried different configs
HSE+PLL1 - 96MHz
BRP - 1
TSEG1 - 149
TSEG2 - 50
tq per bit - 200
HSE+PLL1 - 48MHz
BRP - 1
TSEG1 - 74
TSEG2 - 25
tq per bit - 100
On these two FDCAN raise error passive flag and goes to idle, no data received.
HSE+PLL1 - 48MHz
BRP - 6
TSEG1 - 59
TSEG2 - 20
tq per bit - 80
HSE+PLL1 - 48MHz
BRP - 12
TSEG1 - 29
TSEG2 - 10
tq per bit - 40
HSE+PLL1 - 48MHz
BRP - 24
TSEG1 - 14
TSEG2 - 5
tq per bit - 20
HSE+PLL1 - 12MHz
BRP - 3
TSEG1 - 29
TSEG2 - 10
tq per bit - 40
On these configs behavior is the same: receive - just fine, transmit - fail as I mentioned above.
I found that FDCAN1 and FDCAN2 behavior on same configs is different. Some of FDCAN1 packets reaches other nodes, I see some discontinous reaction of executive mechanisms.All packets transmitted from FDCAN2 are discarded with error.
2022-04-06 06:46 AM
Check your Tx path: GPIO pin, transceiver, etc..
+ Check the power supply of your transceiver + its stability