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H7 ADC Gapping - Voids in the digital output

PWalt.2
Associate II

Hardware: H750 Revision V

Peripheral in Question: ADC 1 and 3

Capture rate: 860Hz

ADC Kernel Clock: 2Mhz

Channels Converted: 5

ADC Conversion overlap: NO

Transfer Protocol: DMA

ADC Conversion Trigger: TIM

We are using ADC 1 and 3 to capture analog pressure sensor readings. We observed a gapping phenomenon in the output data where the ADC failed to output data in specific ranges consistently.

We discovered that using the ADC_CALIB_OFFSET was incorrect and switched to ADC_CALIB_OFFSET_LINEARITY. We also calibrate every power cycle and account for temperature drifts. Despite all of this, on approximately 25% of the units we still see this gapping with the same version of firmware.

*Update - Adding in ADC Configurations via images

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0693W00000WJG9yQAH.jpg0693W00000WJG9jQAH.jpg

16 REPLIES 16
PWalt.2
Associate II

Update:

  • An ADC kernel clock of 2Mhz appears to induce this phenomenon. When I increase the kernel clock via the dedicated PLL up to 100Mhz, this gapping issue appears to resolve itself almost entirely. Thoughts? It was my understanding that the getting started manual recommended an ADC kernel clock of <= 25Mhz

AScha.3
Chief II

you driving the adc almost at its extreme frequ. , hi or low end.

what its doing, if you choose lets say 20MHz adc clock and 7.5 or more sampling time ?

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MasterT
Senior III

You didn't tell what is sampling time. If it's long enough x 5 channels , there is a possibility adc has no cycles to complete some conversions

Running the ADC's at 20Mhz and 32.5 sampling cycles works well as well.

Sampling time is set to 32.5. I have tested with other sampling cycle counts as well. If I am asking for conversion faster than it can serve, I will see my sampling rate decrease as it takes longer to convert.

Where is the Reference voltage for ADC coming from?

Seems, like an interference from other peripheral, have you check for Errata docs?

i asked for this, because this is in the "optimum range" of these kind of adc;

just the way, they are working (charge-redistribution successive-approximation adc),

read: https://www.ti.com.cn/cn/lit/an/slyt176/slyt176.pdf

you can expect: they will loose precision when driving at (too) high clock speed, because the charge on the test-caps has no more enough time to come to a 100% balance (R-C time is never zero !), same loss of precision will happen at low clock speeds , depending of the temperature and the leakage of all parts on the die, here the 0.1 pF caps, that must keep their charge to 1/65000 ( = 15 ppm); so not much time, until even many Mega-Ohm isolation will dischsrge in short time.

so: obviously the optimum function is to expect, when running at 1/2 or 1/4 of absolute maximum frequ.

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We have cross referenced the Errata. this issue persists across all channels on both ADC 1 and 3. We also tried running just one ADC, and disabling LSE as per the errata's indication.

The analog reference runs off of a voltage reference (PN: LT1461DHS8-3.3#TRPBF) for added stability. There are also filters added to the ADC input lines.

That makes sense for the high end but for the low end, shouldn't a slower adc kernel clock help, not hurt with adc performance? It would imply that sampling capacitors have more time to charge to the incoming voltage.