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PWalt.2 · 2022-11-22

Hardware: H750 Revision VPeripheral in Question: ADC 1 and 3Capture rate: 860HzADC Kernel Clock: 2MhzChannels Converted: 5ADC Conversion overlap: NOTransfer Protocol: DMAADC Conversion Trigger: TIMWe are using ADC 1 and 3 to capture analog pressure s...

PWalt.2 · 2022-12-02

Here is a spread sheet of when/where the gaps and clips occur. The numbers under the gaps are the minimum and maximum values around a gap. As in, the low number is the bottom of the gap and the larger number is the top side of the gap. This data was ...

PWalt.2 · 2022-12-02

Here is a screenshot of the DNL for the 16 bit ADC. I am seeing +1.7/-1. I am assuming this means you can have a swing of +/- 2LSB worth of data. That doesn't seem to add up to the gapping we are seeing. Or am I misreading this? We don't need absolut...

PWalt.2 · 2022-12-01

And the explanation of the process issue is that a slow clock speed could allow some of the capacitors of the SAR to discharge before the comparison and DAC operations are performed? I'm trying to get to an explanation of how the process fails. The g...

PWalt.2 · 2022-12-01

That makes sense for the high end but for the low end, shouldn't a slower adc kernel clock help, not hurt with adc performance? It would imply that sampling capacitors have more time to charge to the incoming voltage.

PWalt.2 · 2022-12-01

We have cross referenced the Errata. this issue persists across all channels on both ADC 1 and 3. We also tried running just one ADC, and disabling LSE as per the errata's indication.The analog reference runs off of a voltage reference (PN: LT1461DHS...

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H7 ADC Gapping - Voids in the digital output

Re: H7 ADC Gapping - Voids in the digital output

Re: H7 ADC Gapping - Voids in the digital output

Re: H7 ADC Gapping - Voids in the digital output

Re: H7 ADC Gapping - Voids in the digital output

Re: H7 ADC Gapping - Voids in the digital output