Glitch value for DAC in the STM32G071

[Akoli.2]

Hello.

I can't find Glitch value for DAC in the STM32G071 documentation, and also what type of DAC is implemented in the MCU: R2R, resistor string, etc.

Where can I find the information I need?

[Kamil Duljas]

DAC characteristic:

https://www.st.com/resource/en/datasheet/stm32g071cb.pdf

Probably page​ 92-97

But not know information about DAC implementation ​

[Kamil Duljas]

@Community member​ did you resolve issue?

[Akoli.2]

No. The datasheet and reference manual do not have data on the Glitch value of the DAC when changing the code. Of course, I looked at these documents before asking my question. I think even the type of DAC in STM32 is very secret information and the Glitch value is not normalized in any way and can be anything.

[Peter BENSCH]

Well, at least the type of the DAC is mentioned in the data sheet, section 3.15:

The 2-channel 12-bit buffered DAC converts a digital value into an analog voltage available on the channel output. The architecture of either channel is based on integrated resistor string and an inverting amplifier. The digital circuitry is common for both channels.

Regards

/Peter

[AScha.3]

just guessing: DAC is build similar to (SAR-) ADC on chip;

this is called: charge-redistribution-DAC-architecture

see...

https://www.researchgate.net/figure/Proposed-charge-redistribution-DAC-architecture-a-Overall-architecture-b-Operation-in_fig1_224223250

so probably the dac internally switching between 2 charge-redistribution-DAC-switches, to circumvent the drop on charged sample-hold caps.

then you have no "glitch" at all, just the "slewing" time from one voltage-level to another;

and this is given in DS as 3..4us (much too long time, if it would be a R2R dac, so im probably right.)

edit :

ok, Peter told us ... resistor string. :)

[Akoli.2]

Thank you. I've looked at the documentation several times and haven't found this.