2020-03-05 07:29 AM
Hello,
I'm trying to get a SPI communication in between two STM32 running with DMA. One is the STM32F051R8T7 (slave), the other ist the STM32F412ZET7 (master). There is nothing else on this SPI-bus. The best would be, if it runs with hardware controlled NSS. I'm facing various problems here and already tried a lot.
The basic problem I'm facing is, that I want to send multiple "messages" via SPI. A message should be any amount of bytes that are filled into one tx-Buffer and then send via SPI by the DMA. After one message, the data in the tx buffer will get modified and send again and so on.
My code is based on the examples of CubeMX, e.g. STM32F072RB-Nucleo\Examples_LL\SPI\SPI_TwoBoards_FullDuplex_DMA. It is working somehow, but I have some independend issues, depending on which way I go from here:
Best regards,
Christian
2020-04-14 11:44 PM
This all is a recurring theme here. My November 8, 2018 at 7:19 PM post in https://community.st.com/s/question/0D50X00009XkYEnSAN/spi-master-nss-always-low-in-stm32f4 shows that I already have this misconception rooted deeply in my mind... sorry again.
JW
2020-04-14 11:54 PM
Well, I would totally agree if hardware NSS would only work in a specific use case like descibed by you. But is the rising edge of the NSS-signal in this case a "good" edge, or the same slow charging curve like shown above?
2020-04-15 12:48 AM
Yes. As with any wired-OR system, the value of pullup is crucial here, together with any parasitic capacitance.
JW
PS. There's also no provision to prevent collisions. Take it as it is, or leave it.
2020-04-15 01:40 AM
> Yes. As with any wired-OR system, the value of pullup is crucial here, together with any parasitic capacitance.
Well, but that's again my point from the first post: You cannot have a really fast rising edge with a pullup. That's why, the NSS pin is usually configured as Push-Pull