2024-07-18 03:45 AM
Hi everyone,
I am observing some data corruption in an external SDRAM connected to an STM32 F7 FMC peripheral and I am trying to understand what is happening and how to prevent it.
Kind regards
2024-07-18 04:06 AM
The write buffers aren't that deep
The cache would be the thing implementing write-back vs write-thru the former occurring at line eviction.
2024-07-18 04:29 AM
Hi Tesla,
sorry for my ignorance.
If I understand you correctly, my theory is wrong and the issue I am facing is not related to concurrency / timing access from the FMC to the external SDRAM but caching issues. And also that if the caching is set to "write-through" then the issue should not be observable
Could you share how do we control the FMC caching in the STM32 F7 MCU?
How do we check which "write-through" vs "write-back" is set and how do we change it to "write-through"?
2024-07-18 06:04 AM
Is this repeatable? Is the same memory region 0xFF after reading it back? If not, I would expect this is a hardware or signal integrity issue. Is this a custom board? Does not look like a cache issue because it appears in the middle of a large buffer.