About BrMel10

BrMel10 · 2024-07-18

Hi everyone,I am observing some data corruption in an external SDRAM connected to an STM32 F7 FMC peripheral and I am trying to understand what is happening and how to prevent it. Scenario:Configure the FMC to interface with a Winbond external SDRAM ...

BrMel10 · 2024-06-28

APPLICATION OBJECTIVE:The objective is to monitor a high-frequency signal in the range of 0 to 50 MHz from an external device and count the signal pulses every 10 microseconds windows/bins.Platform:STM32F7APPROACH:The current approach is to configure...

BrMel10 · 2023-11-15

Hi everyone Question: suppose one sets up a DMA transfer from a Timer1 register to memory so that it gets executed when timer event is raised. What happens first:the peripheral to memory DMA transfer is executed ?or the Timer registers are updated?...

BrMel10 · 2023-11-14

Hi everyone,I am trying to implement a system that counts pulses that can be as narrow as 20 nanoseconds using an STM32F746 MCU clocked at its max 216MHz.The first thought was: "Can such narrow pulse even be detected by the MCU?"To confirm, and inspi...

BrMel10 · 2024-07-19

I never discard the possibility of a bug in the code but this time it not the case. Context:We developed several boards with two types of SDRAMs: one 8MB and the other 32MB, but both SDRAMs share the same pinout.The issue only manifested itself on th...

BrMel10 · 2024-07-18

Hi TDK,Yes. The behavior is repeatable. When reading back the buffer, the 0xFF are always observable in the same position in the buffer.Yes. The board is a custom one. In an attempt to check whether it could be a cache issue, I tried to configure the...

BrMel10 · 2024-07-18

Hi Tesla,sorry for my ignorance.If I understand you correctly, my theory is wrong and the issue I am facing is not related to concurrency / timing access from the FMC to the external SDRAM but caching issues. And also that if the caching is set to "w...

BrMel10 · 2024-06-28

SOME RANDOM THOUGHTS (even if true not sure how to debug them):Could TIM3 for whatever reason generate a fast stream of TRGO events which TIM1 senses in its ITR and its DMA transfer is triggered.Could this be due to the fact that Timers1 and Timer3 a...

BrMel10 · 2023-11-22

Both previous answers were useful and would mark both as "Accept as Solution" if I could.Thank you!

User statistics

User Activity

FMC: Data integrity in SDRAM

Master TIMER3 -> Slave TIMER1 Synchronization: Slave Timer ETR pulse counting

STM32F746: behaviour of from Timer to Memory DMA transfer when timer event occurs

Noob doubt: Is a timer clock frequency relevant for input edge detection?

Re: FMC: Data integrity in SDRAM

Re: FMC: Data integrity in SDRAM

Re: FMC: Data integrity in SDRAM

Re: Slave Timer ETR pulse counting

Re: Noob doubt: Is a timer clock frequency relevant for input edge detection?