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STM32H745 and ISDRAM - S42S32800J-7BLI communication issue

ABora.4
Associate III

Hello,

In my current project, we are using MCU - STM32H745Xi and integrated with SDRAM - IS42S32800J-7BLI.
As of now, we are accessing 3 location of SDRAM to write and read the data and below are the observations:

  • When we write the data and read it immediately we are able to read it properly and with correct value.
  • When we re read the same location, we get different data that the previous may be corrupted data. Logs for the same are attached for your reference.
  • The SDRAM is configured in CAS latency 3 and operating frequency of the controller for SDRAM is 120MHz.
  • SDRAM timings are set as per above configuration and is verified on the another custom board.
  • We have make 3 proto board and we are facing this issue on 2 boards out of 3.
  • Data lines are kept PULL UP internally(from software) during initialization 
  • If we store the data in non cache region of the SDRAM, the issue is observed as mentioned above.
  • If we store the data in cache region of trhe SDRAM then there is no issue, we get the correct data value except  unwritten location of the SDRAM but after write the data on that location, it shows correct every time.
  • We have also do the same exercise with internal flash of MCU and it always gives us the corrected data.
  • Currently we are using 256Mb memory.

Please find the below attachments for your reference and provide your valuable guidance to resolve it.

Let me know if you need more information.

Regards,

Alpesh

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