Flash wait states meaning

[RKall.1]

Hi i have a generic doubt about falsh wait states:
Say we configured the PLL to run system core clock at 160 M Hz, with flash wait states as 5.

Then is cpu is equvilent to 32 MHZ core performance? (assuming 1 clk/ 1 inst, no ART's)

Could some one help me on this so that i will make my understandings better which helps me to choose the right controller for right application?.

[Tesla DeLorean]

It means the flash accesses at around 27 MHz (35 ns), but it's not accessing bytes, but rather 128 / 256-bit flash lines, thus one read can sustain multiple MCU instructions.

The H7 also has a cache so that hides latency of slower memories.

[RKall.1]

@Tesla DeLorean  thanks for your reply. 
By considering 32 bit instruction and const data access (worst case) with 128 / 256-bit flash lines, it could fetch 4 / 8 instructions/data @ 27 M Hz. So apparently the processor speed is (worst) is 54 M Hz (considered 1 isntruction + 2 const data + 1etc)