Flash layout of STM32G4xx Cat. 3 with less than 512 kByte missing in RM0440

[Andreas Bolsch]

RM0440 table 7, even in rev. 2, does not describe the flash layout of devices with less than 512 kB flash in dual bank mode.

Is there a gap between the two banks is this case or not? The textual description doesn't even mention devices with less than 512 kB.

And STM32Cube_FW_G4_V1.1.0 package doesn't contain any project/linker file for those devices either ...

[Igor Cesko · Accepted solution]

The Table 7 contains information also for devices with 256kB and 128kB Flash memory:

Table 7 name is: "Table 7. Flash module - 512/256/128 KB dual bank organization (64 bits read width)"

So - it is for devices with 512/256/128 KB complete Flash memory.

In the second column is for each bank written:

Bank 1 (256/128/64 KB)

Bank 2 (256/128/64 KB)

So - in dependency from complete Flash memory size depends the given Bank size => each bank has half size of whole flash.

There is address gap between both Banks if the whole Flash size is less than 512kB.

BUT!!! In case of single bank for the same device is there no address gap in address space (see Table 8. Flash module - 512/256/128 KB single bank organization (128 bits read width)). In single bank configuration is the bus width 128-bit instead of 64-bit in dual bank configuration. Physically in single bank organization: first 64 bits are from Bank1 and second 64 bits are from Bank2 , ... (interleaved data from both banks). This organization can be tested: set dual bank mode (option byte), program Bank1 with pattern "0x11", program Bank1 with pattern "0x22", set single bank mode (option byte) - then you can see the memory content in single bank mode as: 0x11111111, 0x11111111, 0x22222222, 0x22222222, 0x11111111, 0x11111111, 0x22222222, 0x22222222, ...

For IAR and Keil (or another compiler/IDE): setting for dual bank devices with less than 512kB memory must be manually adjusted in linker file - split the Flash area into 2 sections. Because default setting for compilers is usually for single bank mode (simply reduced memory address space).

Regards

Igor

[Andreas Bolsch]

Thanks! Maybe the RM could be made more explicit on this topic in the next review? Like in RM0351 and RM394.

[Asantos]

Igor,

Setting the G4 flash to single bank and 128 bits bus width improve the performance of the code running from Flash against the dual bank mode and 64 bits bus width?

Is Single bank mode the STM32G4 Flash default configuration?

What is the advantage of using the Flash in Dual bank mode?

[Igor Cesko]

The 128-bit bus width generally improve the performance. But there depends from the code. Because STM32G4 has ART accelerator which caches instructions (1kB) and in practical applications is the performance almost the same with 128-bit and 64-bit width - if the ART is enabled. But there can be code where the 128-bit width is important (long linear code or large code loops).

From factory is set dual bank mode.

The dual bank mode is useful for safe firmware update or update firmware on the fly - functional running code is in one bank and then we can switch to another bank into which was loaded new code. Dual bank also supports read-while-write feature: code can run from one bank during programming the another bank (for example: to store some data - like into data EEPROM).

If dual bank features are not used in application then is better to use single bank mode - because of 128-bit access. In this case the address space is without gap between banks - if devices with less than 512 kB memory are used.

Regards

Igor

[Asantos]

Igor,

After read the AN4767 "On-the-fly firmware update for dual bank STM32 microcontrollers". I did not understand how to switch between banks. I load my new firmware, also linked to the address 0x08000000, to the bank2 while the application still running on bank1. After that I can change FB_MODE bit to 1 and the CPU will simply fetch the next instruction from the bank2. Without reseting the cpu? The firmware in bank 2 will probably be different. So the CPU will fetch a wrong instruction, or a table.

Ari.

[Igor Cesko]

The firmware change on the fly is tricky - switch must be made carefully. For example the code which performs the switch must be the same on both firmwares and at the same fixed address - because the code should continue in another bank. There are also another specifics (RAM variables used on both firmwares must be at fixed addresses, RAM routines, ... ) - but all is described in details in the AN4767: how to design the firmware and how to compile the firmware for safe switch.

If you do not require "live switch" - I recommend to use reset and start new firmware from the beginning. The "on-the-fly" switch is important in critical applications which should be not stopped (or cannot be switched off) - for example in power supply (for super computer) controlled by STM32G4 or in the running engine. It is dangerous operation which must be perfectly designed and tested.

There is example code for this AN4767 document (simple - but functional code for explanation).

Regards

Igor