fdcan bit time config for classic frame STM32H563VGT6

[DAUSILI]

Hi,
this is myproduct code STM32H563VGT6.

I am configuring the FDCAN2 module.
In particular the bit time using the filed below of the init structure of the HAL handler:
hfdcan2.Init.NominalPrescaler (NBRP+1 of register FDCAN_NBTP)
hfdcan2.Init.NominalSyncJumpWidth (NSJW+1 of register FDCAN_NBTP)
hfdcan2.Init.NominalTimeSeg1 (NTSEG1+1 of register FDCAN_NBTP)
hfdcan2.Init.NominalTimeSeg2 (NTSEG1+2 of register FDCAN_NBTP)
The protocol (and the ST manual rm481 at page 2542) specify that TimeSeg1 max value is 16, TimeSeg2 max value is 8.

In the example FDCAN_classic_frame_example I found this values:

hfdcan1.Init.NominalPrescaler = 1;
hfdcan1.Init.NominalSyncJumpWidth = 62;
hfdcan1.Init.NominalTimeSeg1 = 187;
hfdcan1.Init.NominalTimeSeg2 = 62;

Seems that these value are out of range.
I'm definitely missing something.

can someone explain the meaning of the parameters in the example "FDCAN_classic_frame_example" ?

Thank you.

Regards.

[mƎALLEm]

Hello,

This is a known issue in the FDCAN spec and it was already internally reported on the ticket 193478. 

From the reference manual RM481/page 2575:

page 2571:

The correct bit times:

For Nominal bit time:
- NTSEG1: between 1 and 256 (* tq)
- NTSEG1: between 1 and 128 (* tq)
For Data phase bit time:
- DTSEG1: between 1 and 32 (* tq)
- DTSEG2: between 1 and 16 (* tq)

So the example is correct.

---

As you are using Classical frame you need to set only the Nominal bit time.

Hope that answers your question.

[DAUSILI]

Hi mƎALLEm,
thank you very much for your reply.

For Classical CAN I don't understand how max values for NTSEG1 and NTSEG2 can be so high:
- NTSEG1: 256 (* tq)
- NTSEG2: 128 (* tq)

I attach a screenshot from document "BOSCH CAN Specification version 2.0".
In this document max values expressed in tq are smaller.
Also "Controller Area Network Konrad Etschberger" book page 82 confirm these limits.

For sure my fault, but I don't understand.

[mƎALLEm]

Hello,

I don't know which Bosch spec you get that screen shot from, but you need to refer to the M_CAN.

This is a screenshot from BOSCH M_CAN spec (page 23):

Hope that answers your question.

[DAUSILI]

Hello mƎALLEm,
Thank you for your reply and for the link to the Bosch M_CAN controller document.

I am attaching the document I was referring to in my previous post.
It is the CAN specification version 2.0 part A and B.

Although the ST peripheral I am using is an FDCAN, since I am using it as a classic CAN, I thought I had to follow the instructions provided by the CAN 2.0 specification in terms of bit timing.
From what you're telling me, this is not a constraint.
For tseg1 and tseg2, I can follow the instructions given by the FDCAN.
Is that correct?

[mƎALLEm · Accepted solution]

Ah,

The spec you referred to is for CAN2.0 (bxCAN) not for CANFD (M_CAN/FDCAN).

Meanwhile, you can use FDCAN peripheral in Classical mode by setting only the nominal bit time. The data phase will be discarded even if you configure it.

Example provided in CubeH5 for FDCAN configured in Classcal mode: https://github.com/STMicroelectronics/STM32CubeH5/blob/main/Projects/NUCLEO-H563ZI/Examples/FDCAN/FDCAN_Classic_Frame_Networking/

Hope that helps.

[DAUSILI]

Hello mƎALLEm,

at the beginning of this post I asked this question due to this requirement:

with the limitations defined by the CAN 2.0 A and B specifications in terms of tseg1 and tseg2, I was unable to manage all the baudrates required by my application. For the moment, by appropriately scaling the clock frequency supplied to the FDCAN peripheral, I have managed to comply with the CAN 2.0 A and B specifications. If needed, I will consider the documentation you shared with me.
Thank you.