Fast communication between two STM32U5G9s

Smith_023 · ‎2025-09-14

Hello, I found in the documentation search for STM32U5G9 that some interfaces available for high-speed communication, such as OctoSPI and HexaSPI, do not seem to support slave mode.

The device we are making requires two STM32U5G9 chips, each connected to a display, and these displays need to show synchronized content. Additionally, one of the U5G9s will connect to a CYW55513IUBGT for network/Bluetooth communication, while the other needs to acquire data through high-speed communication between chips, so UART may not meet the requirements.

Therefore, I would like to understand how I can enable high-speed communication between the two STM32U5G9 chips. ...

AScha.3 · ‎2025-09-15

Hi,

how big is distance between chips ? (because hi-speed and more than few centimeters...difficult)

Maybe SPI full duplex (up to 80 Mbit, afaik, see ds) might be the way .

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MM..1 · ‎2025-09-15

Hi Agent Smith ... you omit info about how much data ? Try start reading Parallel synchronous transmission using GPIO and DMA or too USB HS is for U5.

Andrew Neil · ‎2025-09-15

So what, exactly, do you mean by "high-speed" communication?

How fast ?
How much data ?
How far ?
How often ?
etc, etc, ... ?

Does it have to be an STM32U5G9 ?

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.

KDJEM.1 · ‎2025-09-15

Hello @Smith_023 ;

The OCTOSPI and HSPI interfaces are designed to operate in master mode only and do not support a master-slave configuration.

To enable high-speed communication between two STM32U5G9 chips, you cannot use OctoSPI or HexaSPI. Perhaps you can use SPI.

Thank you.

Kaouthar

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Andrew Neil · ‎2025-09-15

@KDJEM.1 wrote:
To enable high-speed communication between two STM32U5G9 chips, you cannot use OctoSPI or HexaSPI.

Unless you use a dual-port RAM ... ?

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.

KDJEM.1 · ‎2025-09-15

Hello;

As mentioned in this FAQ, the QUADSPI/OCTOSPI/HSPI/XSPI interfaces work only as masters. The interfaces do not support full duplex. Therefore, it cannot send and receive data simultaneously.

Thank you.

Kaouthar

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Smith_023 · ‎2025-09-15

Hello, the distance between the chips can reach about 10 cm. Thank you for your suggestion; I haven't tried running SPI at 80 Mbit speed before, but I will give it a try.

Smith_023 · ‎2025-09-15

Hello, I apologize for not providing a detailed explanation of what “high speed” means.
I aim to achieve speeds exceeding 10MB/s because I'm developing a low-power, lightweight XR-class device. Significant display discrepancies between the two chips could cause discomfort. Additionally, due to limited ports (DCMI consumes a significant number), the current plan involves one chip handling the EMMC while the other manages the CYW55513IUBGT for network communication. Therefore, this channel must also transfer data received from the network to the EMMC. Communication between chips will be frequent, primarily for display synchronization calibration and data transfer. Regarding the necessity of using the STM32U5G9, it currently appears essential, as only this chip meets the requirements for low power consumption, robust display performance, and extremely compact size.

Andrew Neil · ‎2025-09-15

@Smith_023 wrote:
I aim to achieve speeds exceeding 10MB/s .

Is that bit per second, or bytes per second?

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.