Explanation for NVIC_EnableIRQ(irq_no)

[Aditya Mall]

Posted on May 17, 2018 at 20:19

Hello EE verse,

Can anyone explain the below implementation ?

I did see the reference to this function in the cortex_m4 generic reference manual but couldn't understand how the register is mapped.

Also no sure why in NVIC->ISER, IRQn (6 in my case) will be right shifted by 5? can you explain the logic?

__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn){      if ((int32_t)(IRQn) >= 0)       {          NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));       }}

-AM

#interrupts #core_m4 #nvic #nucleo64 #stm32f401re

[Tesla DeLorean]

Posted on May 17, 2018 at 20:42

The >>5 is DIV32 the & 0x1F is MOD32

The NVIC has an array of 32 bit flags arrayed over multiple words.

IRQ6 with be Bit 6 in Word 0

ISER[IRQ / 32] = 1 << (IRQ % 32); // Write the bit position into the Set/Enable register

ie ISER[0] = 0x00000040;

[henry.dick]

Posted on May 17, 2018 at 22:14

It becomes quite easy to understand once you put the code side by side with the reference manual on the core