2022-04-11 06:32 AM
In the manual P 263:
Bits 27:24 MCOSEL[3:0]: Microcontroller clock output
Set and cleared by software.
0000: MCO output disabled, no clock on MCO
0001: SYSCLK system clock selected
0010: MSI clock selected.
0011: HSI16 clock selected.
0100: HSE clock selected
0101: Main PLL clock selected
0110: LSI clock selected
0111: LSE clock selected
1000: Internal HSI48 clock selected
But the real order is
0000: MCO output disabled, no clock on MCO
0001: LSE clock selected
0010: LSI clock selected
0011: HSE clock selected
0100: HSI16 clock selected.
0101: Main PLL clock selected
0110: SYSCLK system clock selected
0111: MSI clock selected.
1000: HSI48 clock selected
This is the order in the CubeMX mux setting for the MCO output.
Solved! Go to Solution.
2022-04-11 02:21 PM
Sorry...
I misread my own code from a few years ago.
There is no error in the manual.
2022-04-11 06:50 AM
@Nikita91 ,
Are you sure the order in CubeMX also implies value of the bitfield?
JW
2022-04-11 08:42 AM
I'm only saying that the order in CubeMX matches what I observe on pin PA8.
When I put 1 in the RCC->CFGR / RCC_CFGR_MCOSEL field, I get a frequency of 32768 and not 120MHz.
I think the people who wrote the HAL followed the RM, the people who did MX followed the hardware specification.
2022-04-11 09:45 AM
> When I put 1 in the RCC->CFGR / RCC_CFGR_MCOSEL field, I get a frequency of 32768 and not 120MHz.
That sounds convincing indeed.
I would like to confirm, but don't have an 'L4+ at hand... :(
JW
2022-04-11 12:27 PM
If this is true, it could be the same for L4 series. I'll test it on L432 and report.
2022-04-11 02:21 PM
Sorry...
I misread my own code from a few years ago.
There is no error in the manual.
2022-04-11 03:57 PM
Thanks for coming back with the solution.
You may perhaps select your post as Best so that thread is marked as solved.
JW