2023-10-08 11:28 PM
I have enabled two interrupts. First one is EXTI for GPIOA0 Pin and another is UART3 for RXCALLBACK.
I want to disable EXTI interrupt when UART interrupt is triggered and enable again EXTI interrupt once the task is completed.
I used __disable_irq(5) to disable the EXTI interrupt but I am seeing below error on building the project.
./Drivers/CMSIS/Include/cmsis_gcc.h:129:27: note: declared here
129 | __STATIC_FORCEINLINE void __enable_irq(void)
| ^~~~~~~~~~~~
Kindly suggest. I am still learning the interrupt handling. Not sure where I am wrong.
2023-10-09 01:30 AM
Hello @Nico3,
the __disable irq() function disables all interrupt, HAL_NVIC_DisableIRQ(IRQn) is probably what you're looking for!
Try that out, and keep us updated!
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2023-10-09 01:42 AM
why disable exti ?
just put higher priority for uart , than exti. so exti will never disturb uart . :)
2023-10-12 11:03 AM
2023-10-12 11:06 AM
yes, I would like to implement but m confuse about priority implementation. I see vector table mentioned in datasheet has priority for each interrupt. But STM32 cubeide shows default 0 priority and can be selected in between only 0,1, 2.
Please clarify.
2023-10-12 11:23 AM - edited 2023-10-12 11:23 AM
Depends on how the NVIC is configured to group them, the M3/M4 implement 4-bits for priority/preemption levels and how those are split, 2-bits for each gives 4-levels.
Even at the same priority level the NVIC shouldn't call another interrupt whilst servicing the current one, it should simply tail-chain it next.
Not 100% sure on the CM0 STM32F0, perhaps look at ST's Programming Manual for the CM0(+) parts, or perhaps Joseph Yiu's treatment of the NVIC via one of his Essential Cortex-M books related to the CM0
2023-10-12 11:26 AM
2023-10-12 01:01 PM
Honestly there is no point in using the HAL bloat like the HAL_NVIC_DisableIRQ()/HAL_NVIC_EnableIRQ() functions. Just use the normal ARM CMSIS provided NVIC_DisableIRQ()/NVIC_EnableIRQ() functions.
2023-10-16 05:06 PM
thanks a lot ...Joesph guide gave me some clarity on NVIC..