2022-01-21 07:08 AM
Hello
I am trying to delay a 1Hz digital signal.
I would like to generate a delay varying from a few microseconds to 10 ms.
I tried to use ETR, TI1_ED and PWM input but I didn't manage to found out how to do.
Does anyone has an idea on how to proceed?
Bests
2022-01-22 04:00 AM
There is no hardware to do it without software.
Set up input capture on one channel, and enable interrupt from it. That will be the input.
As output, set up other channel to compare output - don't need to set a particular mode in TIMx_CCMR.OCxM yet, just set up the pin for AF/TIMx_CHx, and enable that channel in TIMx_CCER.
Enable timer's counter by setting TIMx_CR1.CEN. Leave it at internal clock; if needed, set prescaler so that at maximum ARR it won't overflow sooner than the maximum required delay.
Then, in the capture interrupt, read out the captured value from TIMx_CCRx, add the required delay, store to the output channel's TIMx_CCRx, read the current input pin's level and set the output's mode in TIMx_CCMR.OCxM to appropriate "set to active/inactive on match".
That's all.
JW
2022-01-22 04:18 AM
On second thought, there may be a purely hardware solution:
The risk associated with this method is incorrect output polarity/inversion, so I'd set up an interrupt upon the first capture, and perform the whole setup including checking/adjusting polarity there.
JW
2022-01-22 07:22 AM
You dont detail how bit width is your digital signal, in teory you can delay for example 8 or 16 bit bus too.
And too if only one bit signal you can use EXTI interrupt as input(s) read event
, then timer or other way to measure delay and out latch...
2022-01-22 08:31 AM
10 us to 10 ms is 1000 samples. Set up a timer to sample the GPIO to DMA at 100 khz. Output the sample N ticks delayed again via DMA.
2022-01-22 09:31 PM
8 bit mcu way: timer running and overflows, get input channel capture interrupt, grab the timer captured timestamp, add your delay, write it on output compare channel. Max jitter will depends on timer run frequency, max delay will be timer overflow period. Once this works, explore a more hardware assisted solhtion.
2022-01-24 12:33 AM
Hello. Thanks everybody for your answers.
I'll give it a try and give a feedback.
Bests