Cortex M33 fault handlers not being executed

[David Littell]

Fault handlers that work on M4 and M7's aren't being executed on an M33.  The Usage Fault I'm creating (via an undefined instruction) appears to be escalated to a Hard Fault.  The Core stops executing instructions before ever reaching a handler.  Is this an artifact of some M33 security BS and if so, how can it be corrected?

Thanks very much for any insight.

[Tesla DeLorean]

Probably, but "Lockup" is apparently a state..

https://developer.arm.com/documentation/100235/0004/the-cortex-m33-processor/fault-handling/fault-types-reference-table

Perhaps try a divide by zero or unaligned LDRD/STRD.. Might try some of this later, honestly haven't had a reason to explorer, but have L5 and U5 parts.

[David Littell]

Hi Clive, thanks for the reply.  Hope you're well.

The more I read the less I like about this CM33 thing.  It looks like letting any fault escalate to Lockup and having the watchdog pry it out of its hole may be the only viable option.  When somebody asks why the behavior is so different (and so unhelpful) relative to the M4 and M7's I can tell them "next time choose a core that doesn't suck".

[Pavel A.]

Sorry for jumping in. I haven't looked at CM33 good enough, but isn't there a config register similar to CM7, that allows individual handling of these exceptions instead of escalation to HF?

[Tesla DeLorean]

No worries Pavel, these are the things that need many eyes and insights. On the edge of what I'm doing too.

A quick skim of the docs did suggest you can prioritize, enable/disable and flags some of these things. As I recall there was some flag on other CM models with respect to taking, or not, the divide by zero for example.

[David Littell]

Oh, please don't be at all sorry!  I need all the eyes, ears, brains, and insight I can get.  I've looked at a number of docs and have yet to find the "do normal things a normal way" bit.  😉  I never had to touch anything special for the CM4 or CM7 to do sane things but this CM33 pig seems to be of a different ilk.

[Pavel A.]

Have you looked up how to enable individual exception handlers in CM33? if there's a mechanism similar to CM7, just use it. And leave my reply checked )))

[David Littell]

Haha, no check for you!  😉

Maybe I'm just (more) dense (than usual) but I can't find anything helpful in any document (ARM or ST).

[Piranha]

So you have tried the USGFAULTENA bit in SCB_SHCSR register?

https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/system-handler-control-and-state-register

[David Littell]

Hi and thanks for the response.  Yes, even with USGFAULTENA set a Usage Fault still escalates to a Hard Fault and ultimately a lockup.