2024-06-05 09:13 PM - last edited on 2024-06-12 02:59 AM by SofLit
Hello Team,
I need to connect following two devices with STM32H753ZIT6.
1. NAND Flash- MT29F64G08AFAA
2. RTC SRAM- DS1747WP-120IND+
Kindly review the attached schematics & let me know if any changes are required.
I am little worried about write protection pin (W/P# - pin 19) in NAND flash as there is no specific pin in FMC for it. so have connected it just with one of the I/O pin of STM controller.
same issue is with the RST# pin in RTC SRAM.
Thanks in advance.
Rohit
Solved! Go to Solution.
2024-06-12 03:20 AM - edited 2024-06-14 02:53 AM
Hello,
I'm trying to answer the two original questions:
1- I am little worried about write protection pin (W/P# - pin 19) in NAND flash as there is no specific pin in FMC for it. so have connected it just with one of the I/O pin of STM controller.
That's correct. No write protection pin in FMC you need to manage that by GPIO pin. I don't think the write protection is a part of the FMC protocol.
2- same issue is with the RST# pin in RTC SRAM
Either you connect it to NRST pin of your MCU or manage it via independent GPIO pin. depending where that chip needs to be reset.
Hope I answered your questions.
2024-06-06 08:24 AM
Hello
Please provide the schematic for the connection of the MT29F64G08AFAA NAND Flash and DS1747WP-120IND+ RTC SRAM to the STM32H753ZIT6 so I can review it.
BR
KW
2024-06-06 09:02 AM
I am not quite sure what you are trying to do but MT29F64G08AFAA is 64 Gbit
All 32-bit operating systems have a 4GB RAM limit
For the RAM just see any schematic of the discovery boards with RAM
W/P is just write protect you connect it to any IO PIN, you just keep it HIGH if you want to write to it.
2024-06-06 09:11 AM
But presumably it's a block access device, not placed in linear memory, not directly byte addressable, and the block count / LBA will fit within the 32-bit range
Pentiums in 32-bit mode had a memory address space of 36-bit
2024-06-06 10:33 PM
Thanks for the reply.
What is the maximum memory capacity that can be interfaced with the FMC controller on the STM32H753ZIT6?
2024-06-06 11:40 PM
The individual decode widths for the FMC are 64MB and 256MB
NAND memories only uses a handful of decode addresses and can hide 100's of GB behind that as they are block access devices.
Could perhaps find 1TB eMMC you could access via SDIO/SDMMC with 6 pins..
2024-06-10 03:40 AM
Sir,
I am not getting this clear may be due to lack of knowledge about these devices. Let me put it in this way.
Is it possible to interface following 8GB NAND flash with the STM32H573ZIT6 in Parallel interface?
P/N: MT29F64G08AFAA
I am aware of FMC controller in this series but i am not sure how much capacity of NAND flash I can parallelly interface with this controller as as it is having 26 address lines which shows it can support only 64MB of flash. But I believe this can be increased by some multiplexing technique.
Thanks
2024-06-10 05:36 AM
The Memory doesn't have a 26-bit address pin interface.
You just have to decode, or use a couple of address bits within the 64MB F(S)MC decode window, ie 0x64000000..0x67FFFFFF, to drive the ALE / CLE pins to latch Address and Command values via the DATA BUS, and then push/pull data from a FIFO (~4KB), that accesses a block in the larger NAND array.
Accessing all 64Gb / 8GB of this memory, or the 128Gb / 16GB should be materially the same.
You can't execute from this memory, as it's not directly mappable, It works more like a HARD DRIVE.
https://www.mouser.com/datasheet/2/671/micron_technology_micts02805-1-1759154.pdf
2024-06-12 03:20 AM - edited 2024-06-14 02:53 AM
Hello,
I'm trying to answer the two original questions:
1- I am little worried about write protection pin (W/P# - pin 19) in NAND flash as there is no specific pin in FMC for it. so have connected it just with one of the I/O pin of STM controller.
That's correct. No write protection pin in FMC you need to manage that by GPIO pin. I don't think the write protection is a part of the FMC protocol.
2- same issue is with the RST# pin in RTC SRAM
Either you connect it to NRST pin of your MCU or manage it via independent GPIO pin. depending where that chip needs to be reset.
Hope I answered your questions.