cannot use pll stm32f103rb

[ezrab]

Posted on April 17, 2011 at 16:01

cannot use pll stm32f103rb

[Tesla DeLorean]

Posted on May 17, 2011 at 14:31

Perhaps you shouldn't be making presumptions about the initial condition of RCC->CFGR

[ezrab]

Posted on May 17, 2011 at 14:31 but isnt this line disable all assumation? '' /* Select PLL as system clock source */     RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; ''

[Tesla DeLorean]

Posted on May 17, 2011 at 14:31

Printing out the RCC registers in your two conditions might be instructive to understand how the PLL is running at the different speeds.

This line makes a lot of assumptions     // Select PREDIV1 as PLL source and sett PLL mul to 3 (set bit 0)     // for 8*3 = 24 MHz     RCC->CFGR |= RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL_0;