Can TIMx OC DMA events be used to load DACs from memory?

[KHarb.1]

I want to vary the duty cycle of two adjacent DAC values of an STM32G473.  I am using DAC1 channel1 and channel2 for the output. I want to load DAC1s DHR12Rx registers via DMA when TIM3 hits output compare values.  I set up a memory to peripheral transfer for each TIM3 channel and set the CMAR and CPAR registers to the memory location of the DAC values and the peripheral addresses of the DAC DHR12Rx registers.  

I have been able to make this configuration work for making the TIM3 OC events trigger loading of TIM20's CCR registers from memory, but so far, the DMA transfer won't load the DHCR12Rx registers for the DACs.  Are there additional configuration settings to make this work? 

CubeIDE\HAL has configuration options for initializing the DAC in DMA mode, but I need multiple triggers the make the duty cycling work.  

[waclawek.jan]

> By the way, one example I had based a recent (F303) application on uses the DAC dual mode, and employs 32-bit DMA transfers to the specific dual-mode 32-bit DAC register. Modifying it for 1 channel and 16-bit worked fine.

So, after the modification, DMA transferred 16 bits into one part of the same 32-bit DAC register, correct?

Was the other DAC active at the same time? Would you notice if *both* parts of that 32-bit DAC register would be written the same value, instead of just one half of it?

JW

[Ozone]

No, the original example used both channels and targeted the DHR12RD register, which combines the holding registers for channel 1 and channel 2 into one 32-bit register.

I use only one DAC channel in this application, so I modified it to DHR12R1, the holding register channel 1.

When using both channels it surely makes sense to use the combined register, especially if both output signals are related. Which could OTOH make updating the output table (DMA souce) a bit more cumbersome.

[waclawek.jan]

I see, thanks.

JW