Hi,
I'm trying to get LPBAM Low power timer capture to work in a frequency measurement application. The intention is to use LPBAM to write input captures from LPTIM3 to a buffer in SRAM4 while in Stop mode 2. The app loop just sets a wakeup via the RTC of 500mS, then enters Stop Mode 2. On wakeup, it does a few GPIO read/writes and I2C3 writes amongst other things, then loops,
That all works fine, and the system is in Stop Mode 2 95% of the time.
LPDMA1 CH0 is enabled in the non-LPBAM IOC configuration editor in Linked-list and circular mode.
I've created an LPBAM application/scenario with just one queue, and LPTIM3 channel2 set for input capture clocked by external clock (LSE crystal 32.768KHz).
(ScreenShots below)
This passes 'CHECK LPBAM DESIGN' in the editor, and generates code without errors.
I've then added the LPBAM init/build/link/start calls to main before the main loop starts:
/* LPT3App application initialization */
MX_LPT3App_Init();
/* LPT3App application LPT3Scen scenario initialization */
MX_LPT3App_LPT3Scen_Init();
/* LPT3App application LPT3Scen scenario build */
MX_LPT3App_LPT3Scen_Build();
/* LPT3App application LPT3Scen scenario link */
MX_LPT3App_LPT3Scen_Link(&handle_LPDMA1_Channel0);
/* LPT3App application LPT3Scen scenario start */
MX_LPT3App_LPT3Scen_Start(&handle_LPDMA1_Channel0);
The application builds without errors, and when run, still works fine apart from there being no DMA triggered in Stop Mode 2.
I can see this in the debugger: the destination buffer for the captures just doesn't seem to get written to, If I set a brakpoint within the loop, the LPDMA1 registers just don't change, although they look correctly set in terms of addresses and peripheral selection:
LPDMA_C0CTR2.REQSEL = 0xf (15) which is correct for LPTIM3 (lptim3_ic2_dma)
LPDMA_C0SAR = 0x46004834 (the address of LPTIM3 CCR2 register)
LPDMA_C0DAR = 0x28000274 (start of the buffer
LPTIM3 registers:
DIER_input.CC2DE = 0x1 (Capture/compare 2 DMA request enable)
The whole application is using SRAM4:
from the Flash.ld file:
/* Memories definition */
MEMORY
{
RAM (xrw) : ORIGIN = 0x28000000, LENGTH = 16K /* SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K*/
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
}
LPTIM3 count and capture registers are changing between repeated run/break sequences, so I'm pretty sure it is running and capturing, just no DMA trigger.
Does anyone know or can see what might be wrong? I've included screenshots below of the config pages and debugger register dumps.
Thanks for reading this far, and thanks in advance if you can help....
