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Flash ECC ON STM32G0C1

AJ2
Associate

I’m currently working on implementing and testing Flash ECC on my controller. According to the datasheet, the device supports ECC, and I can see that it is managed through the FLASH_ECCR register.

However, I’m facing some difficulty verifying whether ECC is functioning correctly. Specifically:

  • I am unable to find any ECC-related flags in the FLASH status register.
  • I’m not sure how to intentionally generate an ECC error to validate my implementation (e.g., to confirm that error handling via NMI/interrupt is working as expected).

Could anyone please guide me on how to reliably trigger a Flash ECC error for testing purposes on this controller? Any suggestions, references, or example approaches would be really helpful.

3 REPLIES 3
GMA
ST Employee

Hello @AJ2,

Refer to How to write your question to maximize your chances to find a solution post.

If you agree with the answer, please accept it by clicking on 'Accept as solution'.
Best regards.
GMA
mƎALLEm
ST Employee

Hello @AJ2 and welcome to the ST community,

Please read this knowledge base article: Injecting and handling ECC errors in STM32H7 flash memory

It's targeting STM32H7 product but I think the same principle applied to STM32G0 product.

Hope that helps.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.
waclawek.jan
Super User

IMO there are two different kinds of FLASH controllers in the STM32 families with ECC - some do allow rewrites of non-blank FLASH rows (and thus deliberately generate a ECC-faulty row), others don't. IMO 'H7 belongs to the former group, and 'G0 to the latter, so, if I am not mistaken, the method from that article won't work with 'G0.

You can search this forum as this issue came up in the past; or you can also experiment with removing power while performing a FLASH operation (erase or write).

The ECC flags are in dedicated registers (FLASH_ECCR;  and in the dual-bank devices, FLASH_ECCR2), see FLASH chapter in RM.

JW