BKPSRAM corrupted after power cicle

[clemente]

Hello,

I'm using a STM32U5A5VJTXQ MCU and I need to use the 2K BKPSRAM located @0x40036400.

I can read and write without problem the BKPSRAM after power up, but a power cycle corrupt all the content. Strangely, the RTC content: time and registers, are all retained.

Do I have to make a special setting to ensure that the BKPSRAM retains its contents?

Thanks

Best Regards

Clemente

[KDJEM.1]

Hello @clemente ,

Did you activate the tamper ?

Because each source of tamper in the device can be configured to trigger:  2-Kbyte backup SRAM (depending on configuration bit), erased when VDD is present.

If it is the case and according to the RM0456 section 6.3.1 Internal SRAMs features: " The SRAM2 and optionally the BKPSRAM are protected by the tamper detection circuit, and  are erased by hardware in case of tamper detection."

So, to keep data in BKPSRAM while tamper occurs, you need to enable access to the backup domain and to clear the ERCFG0 bit in the TAMP_ERCFGR register using the following API.

Thank you.

Kaouthar

[clemente]

Hello Kaouthar, many thanks for your replay.

We are not using tamper, we want to save logging information on BKPSRAM because the MCU can be completely switched off, with only Vbat active. We don't need them to be deleted, on the contrary: the content must be retained.

Is it possible to do that, without enabling tamper?

Also, I saw in HAL drivers that there is the "HAL_PWREx_EnableBkupRAMRetention" function. I didn't find it in the RTC, RCC or RAMCFG initialization code. Could this be the problem?
Furthermore, in the explanatory comments, in the function source, it is indicated that: "Backup RAM retention in Standby, Shutdown and VBAT should be enabled when the Vcore is powered by the LDO regulator". Could this also be a problem?

Many thanks again Kaouthar

Best Regards

Clemente

[KDJEM.1 · Accepted solution]

Hello @clemente ,

Thank you for this clarification. 

The backup SRAM (BKPSRAM) can be retained in low-power modes and when VDD is off in VBAT mode.

The HAL_PWREx_EnableBkupRAMRetention function is used to enable the Backup RAM retention in Standby and VBAT modes.

So, as defined in this function and also in RM0456 section 10.10.9 PWR backup domain control register 1 (PWR_BDCR1),  when "BREN": Backup RAM retention in Standby and VBAT modes bit is set, the backup RAM content is kept in Standby and VBAT modes.

If BREN is reset, the backup RAM can still be used in Run, Sleep, and Stop modes. However, its content is lost in Standby, Shutdown, and VBAT modes.

This BREN bit can be written only when the regulator is LDO, which must be configured before switching to SMPS.
Note:

- The backup SRAM content is lost in Standby mode without SRAM2 retention. If either RRSB1 or RRSB2 bit is set
in Standby mode, the backup SRAM is also retained.

Thanks and best regards,

Kaouthar

[clemente]

Hello Kaouthar,

---

If BREN is reset, the backup RAM can still be used in Run, Sleep, and Stop modes. However, its content is lost in Standby, Shutdown, and VBAT modes.

I think this is the solution to my problem. ASAP I will do the tests and confirm and approve the answer.

Thanks a lot.

Best Regards

Clemente

[clemente]

Hello Kaouthar,

It works!!!

I added this code inside the RTC Init:

  /* Check if system regulator is LDO */
  if (HAL_PWREx_GetSupplyConfig() == PWR_LDO_SUPPLY)
  {
    /* Enable the Backup RAM retention in Standby mode */
    HAL_PWREx_EnableBkupRAMRetention();
  }
  else
  {
    if (HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY) != HAL_OK)
    {
      Error_Handler();
    }

    /* Enable the Backup RAM retention in Standby mode */
    HAL_PWREx_EnableBkupRAMRetention();

    if (HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY) != HAL_OK)
    {
      Error_Handler();
    }

And now the backup SRAM retain the content after a power cycle.

As a reference I recommend seeing the "PWR_ModesSelection" project example in the "Example/PWR" directory of the "NUCLEO-U575ZI-Q" board.

Many thanks Kaouthar

Best Regards

Clemente