ARM Cortex M7

[DCtech]

I was using stm32f4 on my project but now I want to use the h7 products. I am reading referance manual and watching some videos about the arm cortex m7, but I didnt understand completely about the CPU things. How can I learn the most basic way to understand its memory organization ?

This is one of the things i don't understand:

I also exemine the example of the stm32Cube with h7, every examples start with CPU_CACHE_Enable(); , Should I use the this line in every project and why I didnt understand this function using although reading referance manual ?

[Tesla DeLorean]

Unlike the CM4 the CM7 has a real cache architected into the core design, and it, like the FPU, is off by default and needs to be enabled. The STM32F4 has ST's ART cache but this only serves to hide the slowness of the FLASH memory.

The RM should have a bus diagram showing the topology of the different RAM memories, and their transactional distance from the core, and the peripherals and DMA units the are most closely coupled too.

The H7 design is more complex as it was always supposed to be a dual core device. So for example the main FLASH and SRAM where dual ported. if two concurrent accesses one from each side/port.​

[waclawek.jan]

Reference manual is not dealing with the processor-specific issues; for that, read PM0253 (and for further details, ARM's Cortex-M7 and ARMv7M manuals).

Also, read AN4839.

You may want to read also AN4667 - while it deals with 'F7 rather than 'H7, it may give you an interesting insight to the Cortex-M7 memory-bus-related issues, especially in conjunction with the 'F7-to-'H7 migration appnote, AN4936.

JW

[DCtech]

Thank you for your advice and sources.

I've a little question to understand something.

My source code for f4, this source code enough for f4. If I use the this code on h7, do I have to use this function: CPU_CACHE_Enable() ? Do I need using Caches ?

[TDK]

Cache is an optional feature and does not need to be enabled. Enabling cache will improve performance at the expense of possibly increasing code complexity.

[SofLit · Accepted solution]

Dear @DCtech​ 

I invite you to read:

• The AN4891 "STM32H72x, STM32H73x, and single-core STM32H74x/75x system architecture and performance" may
• AN4667 "STM32F7 Series system architecture and performance"
• AN4839 "Level 1 cache on STM32F7 Series and STM32H7 Series"
• AN4838 "Managing memory protection unit in STM32 MCUs"

For your question about cache enable: the cache is used to increase the performance of the CPU and it depends on your code and data location. For example if ITCM memory is used for code execution, no need to activate the I-Cache (Instruction Cache). If your data are located in DTCM, no need to activate D-Cache (Data Cache).

So, I suggest to refer to Application notes listed above to understand and have an architecture overview around Cortex-M7.

[DCtech]

Thank you for your help. I start by reading all the docs.

[waclawek.jan]

Hi @Community member​ ,

Is there any reason why AN4891 is not in the list of appnotes in https://www.st.com/en/microcontrollers-microprocessors/stm32h7-series.html#documentation nor https://www.st.com/en/microcontrollers-microprocessors/stm32h743-753.html#documentation nor https://www.st.com/en/microcontrollers-microprocessors/stm32h743ag.html#documentation (this is just a random selection of pages where I'd expect to find it)?

JW

[SofLit]

Hi @Community member​ ,

Maybe @Amel NASRI​  can help you to answer that question.

[Peter BENSCH]

Hi @Community member​,

This is indeed strange. However, AN4891 appears on the product websites, so for example with the STM32H743AG. Unfortunately, you have to click Load More several times to see it.

Regards

/Peter