ADC sample rate impossible to set precisely (calculations added)

[Robmar]

I realise that with ADC timer triggered DMA of 32 samples, you can set the timer precisely, but not the ADC​ per sample clock, so the samples get bunched up or stretched in the frame. The number of clocks per sample is limited, adjusting the APB2 clock hardly helps. A bit more flexibility on sample clocks would be really useful, I guess there is no easy solution?

Objective: capture ADC samples spread evenly at 96 KS/s on STM32F407VG with 8MHz xtal

Reference: STM32F406VG datasheet.

Overview:-

To capture samples from two independent ADCs at 96 KS/s, Timer3 is set to generate

an event every 1/3 mS, i.e. 333.3r uS

ABP1 Clk 84 MHz drives Timer3 from a 42MHz clk via a fixed x2 multiplier.

ADC-DMA is triggered and set to take 32 samples:

APB2 (PCLK2 + prescaler /4,/6,/8) clk drives ADCs at 84 MHz: Period 11.904 nS

Okay, so 3,000 triggers of 32 samples pers second.

1. 3K triggers the ADC-DMA every 333.3r uS

2. 32 samples every 333.3r uS gives 10.416r uS per ADC sample.

3. a1) ADC clk at 84 MHz has a clk period of 11.904761 nS or 0.011904761 uS,

  b1) Prescaler of 8 reduces this to 10.5 MHZ, and a clk period of 0.095238088 uS

  c1) Prescaler 6 clk reduces to 14 MHz and a clk of 0.07142857 uS. 

  d1) Prescaler 4 clk reduces to 21 MHz and a clk of 0.04761904 uS. 

  e1) Prescaler 2 (MX deselected not peritted) clk ... 42MHz ...

  b1-R) P8: We need 10.416 uS worth of clocks per sample, giving 109.375008312501 clks at 10.5 MHz

  c1-R) P6: -""-, giving 145.82400291648 clks at 14 MHz

  d1-R) P4: -""-, giving 218.736034997776 clks at 21 MHz

  e1-R) P2: -""-, giving 437.472 clks at 42 MHz (MX deselected)

Each samples takes 15 clks + (3, 15, 28, 56, 84, 112, 144, 480 sample time clks selectable)

Best match: Prescaler 8, our 96KHz sampling rate requires 109.375 clks per 32 sample trigger, subtracting the ADC sample time of 15 for 16-bit conversion = 94.375 clks, nearest selection is Sample time of 84 + 15 = 99, an increase in sample rate by 10.375 clks per sample.

This increase in the sample rate will require a significant non-standard change to my DSP code. A single transfer per trigger would solve this if there was a way that the ADC-DMA could increment the memory address, but so far I can't see that is supported.

[S.Ma]

The number of answers should point that CubeMX should provide adc timing info for users. Ideally inputting needs and crunching the HW register config accordingly....

[Robmar]

Its really no use make generalised non proven comments like that, maybe this chip can do many things, here we should be talking only about exactly how to do things, otherwise its just hearsay, gossip. Thanks but lets leave it there now.

[Robmar]

Yes the configurator could be expanded to calculate sample rate, best values for clock sampling, timer triggers etc., but I think the main failing is a lack of clarity in the help (i) that appears, much of which is missing for many settings, and rather jargonised for others.

The reference manual I downloaded has 1755 pages, its a "city" of a chip, and the documentation needs to give clear usage examples otherwise there will be less uptake of the chip in designs by engineers who find easier solutions elsewhere. The CubeIDE is also a bit unstable, debugging launches and before its loaded it displays the current execution of whatever old code is running on the connected chip, which is confusing, this needs to be blocked until the new code is downloaded.

Also after every new compile debug fails, and it has to be launched again. These are basic bugs and easy to fix.

[Piranha]

I wrote "most likely" because I have not used that particular feature. Just saw those features in the reference manual and wrote the key registers and bits for you so that you know from where to start looking for more information on those features.

Just in case... ADC_CCR is not ADC_CR2, but they both have a DDS bits.