ADC DC-bias auto-adjusts above 0 volts on F4 and H7, is there any documentation?

[Robmar]

Both F407 and H743 ADC input add DC-bias to AC connected inputs, very handy, but I would like to have the specifications for this feature, perhaps even a circuit diagram explaining how the MCU averages the AC input above ground as needed.

I have read the Intro to ADCs AN4861 and the datasheets but must have overlooked the relevant information.

[waclawek.jan]

>>  ADC sampling capacitor is during conversion charged to an unspecified potential (maybe VREF+/2, maybe not, I am not an expert), which it then dumps into your decoupling capacitor. Under certain circumstances that might mimic DC bias.

> Sure, but as the topic states, I'm looking for technical facts, not gossip!! haha. This needs to be detailed, and I can't find any real details on the ADC input circuit.

That's not gossip, that's the facts, and that's all of them, repeated through the DS and ANs. The ADC input circuit consists of one single capacitor (you'll find its capacitance in the DS), and a switch, which connects it during sampling period to the input pin.

Sure, there are protection circuits with leakages and other surrounding sources of leakage and crosstalk. Leakages are specified in the DS, too (e.g. +-1uA in case of 'F407, although that's a max. for all sorts of circumstances;  for pin set to Analog it will be significantly less, e.g. 'F303 specifies +-0.2uA, it's not specified separately for 'F407 as it's not intended typically for analog usage, and there are costs associated with this kind of specifications, as the manufacturer has to test them). Note, that it's given as +-, i.e. there's no single specified "source voltages", as this leakage adds up from various sources, and they again vary according to circumstances (e.g. there's a contribution from the neighbouring pin, so the leakage depends on how that pin is set up and used). Btw. you have leakages in your circuitry (decoupling capacitor, PCB itself together with whatever surface impurities present such as soldering residui), too.

So, the DC "bias" you see accidentally adds up from these leakages and the charge dumped from the sampling capacitor during conversions. It depends on the particularities of your application.

Your input circuitry has to be designed so that whatever the actual leakage is, and whatever charge state of sampling capacitor at the beginning of the sampling period is, during the sampling period the input circuit delivers the charge needed to charge/discharge the sampling capacitor to the voltage you want to measure. Again, this is the full information you need.

If this information results in the corollary that the decoupling capacitor alone won't cut it, then that's it. Btw. this information also tells you, what value of bias resistor you need to maintain a chosen DC offset. That resistor together with the decoupling capacitor (and its leakage) of course introduces a LF rolloff; if that won't suit your purpose, again, that's it, and you have to design a different input circuit arrangement.

JW

[AScha.3]

@Robmar , 

1. there is NO dc-bias circuit on adc inputs. Thats why there is no information about. :)

2. as @TDK  and @waclawek.jan  explained, you might get some dc-drift or dc-level-shift by the side-effects from protection diodes and remaining charge, coming "back" from the adc sampling cap. this is common to all "modern" adc, read about how they work (charge redistribution SAR ADC  -> https://www.ti.com.cn/cn/lit/an/slyt176/slyt176.pdf  ). Always on start of a adc conversion the sampling cap is connected to the selected pin and of course it has any voltage, just the "remains" from the sar process. This could be zero, = gnd level, if the sequencer inside the adc-block has a discharge step after conversion, but most adcs dont have this, so they come back with any voltage, thats on this sampling cap and the order is: your input has to be so low in impedance, that this cap is charged in chosen sampling time to the applied input voltage (with desired deviation, according to the adc resolution). I tested this on some adcs, just to see, what they do. If you want to test/proof also, just connect a cer.cap , maybe 10nF , from adc input to gnd, nothing else there. then let the adc convert, 1000000 x , and watch its conversion result - and then you see, at which voltage the sampling cap comes "back" from conversion. But be aware, this voltage might change with used sampling time and sample rate !

3. the dc-bias in these adc is just and only (!) a value, thats subtracted from conversion result, so you can get a int instead uint as adc result. The hardware to make/fix any dc offset is up to you .

4. for reliable and reproducible adc input dc level, drive the input within its bounds gnd-avdd at low impedance source with fixed dc level, that you want (1/2 avdd probably). And no, 2 resistors as dc bias from avdd to gnd , will not increase noise or something; just think about the noise currents of these resistors and your (many orders) lower input impedance you have to apply at the adc input.

[Robmar]

You wrote "I am not an expert", "I think...", I wrote "I need hard facts", so thanks for your view.

[Robmar]

Dooh, I know there is no DC bias circuit per-se hence as I wrote, our board has bias resistors.

If you don't have ST printed hard facts, thanks for your view, but it's not what I´m looking for.

[Robmar]

I'm seeing the unconnected ADC direct inputs floating at around 0.6 volts actually, double the figure you give, why would that be?
You say there are other solutions available to remove this uncharacterised DC bias, but what other solution could effectively work in our real world application?

[waclawek.jan]

I took the code from https://community.st.com/t5/stm32-mcus-products/adc-in-stm32f446re/m-p/613434/highlight/true#M228331 and modified it so that it performs conversion infinitely. On a 'F407 Disco, this results on a cca 0.6V on PA1 (which is not connected to any other circuitry on the 'F407 Disco, just the pinheader). It's a "steady" 0.6V, with no visible spikes from sampling, so it could be assumed, that that's the voltage to which the sampling capacitor is charged during conversion, dumped to the parasitics of the pin during the repeated conversion.

Then I modified the code further so that it performs one conversion, waits cca 250us then performs second conversion and then stops. The resulting waveform is here:

The "stable state non-conversion" DC offset is cca 40mV, that's given by the leakages. The charge dumped from the sampling capacitor to the parasitic capacitance (pin and tracks and the probe and scope input) increases its voltage by around 130mV which is around 1/5 of what we assume is on the sampling capacitor at the end of conversion (and we assume it won't leak significantly between end of conversion and start of next conversion's sampling), so if the sampling capacitor is 6pF, the parasitics are around 30pF (the pin's parasitics is given as 5pF, scope's input is spec'd at 18pF probe is 1:10 and its input is spec'd at 14pF, so that's together with some track etc. parasitics is around correct). This discharges to the leakage with tau of cca 200us, so the leakage is cca 6MOhm; but there's 10MOhm of scope+probe, so the pin's true leakage is at around 10MOhm too, or around 0.3uA at 3V, which again sounds about right.

JW

[Robmar]

As I mentioned earlier, 0.6v is what I am also seeing on the F407 disconnected ADC inputs in continuous mode.

The one shot and wait mode is really not helpful in anyway for any application that I can think of, certainly not for fast signal conversions.

I guess there isn't an expert on the ADCs available who can really answer this point, ST often sub-contracts ADC design, USB too, so there are no experts in house.

There probably isn't a good solution, as the application note on ADCs optimisation says, the ADCs are not perfect.

That said if any ST engineers have any hard facts and the ideal solution, please post.

[TDK]

> I'm seeing the unconnected ADC direct inputs floating at around 0.6 volts actually, double the figure you give, why would that be?

I never said it would bring it up to 0.3 V. Perhaps re-read.

> There probably isn't a good solution, as the application note on ADCs optimisation says, the ADCs are not perfect.

You do realize that NO ADCs are perfect, right? I'm not sure why this is such a revelation to you.

[Robmar]

Well son, I guess that having 34 years in the industry has taught me that understanding the details, results in more reliable products, something that ST seems to have forgotten or lost interest in.

I wouldn't have imagined that ST's MCU ADC would leak sufficient current to produce a 0.6v positive bias on the inputs, so it good to have a better understanding of the issue.

I am very disappointed with ST for it's poor support, for pushing out patchy, incomplete, 8 years out of date drivers (USB), and in my opinion, which you can of course disagree with, ST's management have been riding the gravy train for years at customers' cost.

[Piranha]

So that app note says the ADC input circuit is "not perfect" that the input switch has capacitance on the two transistors, and "Practically the firmware must not program the ADC in continuous mode but only in single mode and must ensure that there will be a time gap between conversions with duration
equal to tC."

So and how can we do that when sampling two signals at 384 KHz?

---

You are misunderstanding something here. First, the sampling capacitor and sampling time are not some "imperfections", but the base principles, on which the SAR ADC operates. Second, the continuous mode doesn't skip the sampling time (no mode does it), because it is the required "time gap" you are talking about. All of the documentation clearly tells that Tconv = Tsampl + Tsar.

At 384 kHz conversion rate the period is 2,6 us. Depending on ADC clock frequency and the configured number of sampling cycles, you will have some 2 us or more of a sampling time available. Knowing that and the necessary resolution one can calculate the maximum allowable time constant and output impedance of the driving circuit, which will be somewhere in the range of 30..50 kR.