EVSPIN32G4 - current measurement burst noise at high RPM

[grisharevzin]

Hi everyone!

I'm evaluating STSPIN32G4 for driving a small 6 kRPM 28-pole PMSM (up to about 30A load current - it's driving a propeller, 0.06 mH inductance, about 160 kV). Generally the performance is quite good, but I have noticed frequent STOPLL faults above a certain RPM. I tried many different tunes for the STOPLL but it didn't resolve the issue, and I went deeper. 

Turns out, above a certain RPM (~5k) bursty artifacts begin to appear in current measurement (In I_A, I_B and everything "above" it) and BEMF reconstruction becomes unreliable which I think upsets the STOPLL phase detector.

This only happens:

• above a specific RPM
• on a loaded motor
• appears roughly where overmodulation starts to kick in
• the "critical" RPM after it starts to appear go down if PWM frequency is increased 

I'm guessing it has something to do with the timing of current sampling (it probably samples the current at an invalid interval? or is it because of the distortion introduced by overmodulation?), and would appreciate pointers on where to dig further.

[GMA]

Hello @grisharevzin, 

Thank you for your problem report.
Just for confirmation, does it mean that without Over Modulation, the issue is not visible?
Which version of MC workbench are you using?

[grisharevzin]

Hi @GMA,

Thanks for the response!

The version is MCSDK 6.3.0.

Without overmodulation I don't see the issue indeed but I'm also unable to reach the required speed without it (it goes up to about 4.8 kRPM wihtout overmodulation and our application range is 6 kRPM). The issue appears at about 5.2 kRPM with 30 kHz PWM frequency and at about 4.7 kRPM with 80 kHz PWM frequency.

I have also noticed that the T-rise & T-noise parameters in the FOC Wizard -> Current Sensing influence the RPM at which the problem appears (default T-noise is 1200 ns, and setting it to 100 ns moved the "critical" RPM to 5.7k) but I can't find them in the documentation and it's not clear what I'm changing here (though I guess it has to do with the timing of the exact moment when the ADCs sample the shunt voltage).

[GMA · Accepted solution]

Hello @grisharevzin;

As shown on documentation available through "Workbench tool">About>Documentations>Documentation>"User manual" tab, "Overmodulation" link, "3. Over-modulation example", over-modulation increases the total harmonic distortion due to the non-possibility to sample two phase currents at a given period.
Is-it possible, for your use case, to use 6-Step Driving Algorithm that is also available on EVSPIN32G4 platform?

[grisharevzin]

Hi @GMA,

Thanks for pointing in the right direction.

Indeed, Trise and Tnoise are detailed in "Current sampling in three-shunt topology using two A/D converters" in the documentation, in cases 2 and 3.I was able to increase the max speed somewhat by adjusting Tnoise (it's probably best to do this with a scope...) -- or by reducing the PWM frequency.

I take it that overmodulation isn't taken into account in this field in the Workbench?

[GMA]

Hello @grisharevzin,

You are right, "Max Modulation" index value does not take into account "Over Modulation" feature.

[grisharevzin]

Following up on this topic -- maybe this may be of help to someone later -- it turned out that these faults, in our case, have been caused by ADC input saturation, not by overmodulation. With our motor, we go significantly above the rated current for the evaluation board (55 A vs 20 A on EVSPIN32G4). That in itself is fine if temperatures are closely monitored and some extra cooling is applied to the board's heatsink. But at a certain current the ADC's input will go into saturation.

We resolved this by reducing the op amp gain (R53 / R50 et cetera on the EVSPIN32G4) to 2.4 from the default 7.3. This has a drawback of very noticeable ADC quantization at low currents and lower minimal speed, but the STO/PLL works surprisingly well even with these measurements (250 RPM in our case): 

It can also be resolved by reducing the value of the shunt resistor, but we didn't test this yet. Should theoretically trade ADC quantization noise for electrical noise?..

Anyway, advising that such peaks on polar High Frequency plots might be indicative of ADC saturation: