Dear Sir,
When I configure the clock for the STM32H5, I found that the CPU Clock doesn't match the actual result of the dividers. For example, in the figure showing my current configuration, considering the red path, my clock source is from HSI (64/2 MHz), then it goes through a divider (/2), a multiplier (x31), and another divider (/2). The SYSCLK should be 248MHz, not 250MHz. Is 250MHz just an approximation? Could this cause any discrepancies, such as in the Timer counting?
When designing my system, should I use the actual value of 248MHz instead of 250MHz?
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Accepted Solutions
Hi all,
I have already found the cause. It was because the PLL was set to fractional mode, and the fractional value was set to 2048. We can find the description on RM0481
Hi all,
I have already found the cause. It was because the PLL was set to fractional mode, and the fractional value was set to 2048. We can find the description on RM0481
