SVD errors on STM32H503

[hijax_pl]

Using python I have written small app to convert SVD V1.4 into assembly include. Then I started to write assemby code using RM0492 Rev2 .

For the peripherals I use (RCC,ADC,GPIO,GPDMA,TIM,USART) I have found that there are few errors in the SVD file, some typos etc.

Namely:

RCC_CCIPR5 register has only 2 fields described, no info about FDCANSEL, DACSEL & ADCDACSEL

RCC_CFGR regsiter shall be named RCC_CFGR1

For RCC_PLL1CFGR & RCC_PLL2CFGR there are DIVMx while should be PLLxM

[STTwo-32]

Hello @hijax_pl 

Thank you for repoorting those typos. I'm escalating the second and the third points as they are for correction. But the first point, i find that we have a typo only on the name and discription of the bit values for DACSEL.They others looks fine on my side.

Best Regards.

STTwo-32 

[hijax_pl]

Yes, my mistake.

I have filtered out DAC & FDCAN as peripherals but also from RCC defines.

And yes, DACSEL is DAC1SEL in reference manual.

[hijax_pl]

Do not know if I shall open new thread but anyway.

(1) Why TIM1_SMCR and TIM2/3_SMCR have different naming convetions for SMS / TS fields?

i.e. for TIM1_SMCR there are SMS/SMS_1 and TS/TS_1 and for TIM2/3_SMCR, SMS1/SMS2 and TS1/TS2 respectively.

(2) Also TIM1_SMCR_TS_1 field has no enumerated values, while for TIM2/3_SMCR_TS2 there are, but wrongly described. TIM1_SMCR_TS & TIM2/3_SMCR_TS1 has enums for the range 0..7 only, ie. the TS1 field itself.

As in the RM those fields must be combined, I think the easies way forward would be to provide enums only for the TS1 field, and add missing values:

B_0x10000:Internal Trigger 4 (tim_itr4)
B_0x10001:Internal Trigger 5 (tim_itr5)
B_0x10002:Internal Trigger 6 (tim_itr6)
B_0x10003:Internal Trigger 7 (tim_itr7)
B_0x10004:Internal Trigger 8 (tim_itr8)
B_0x10005:Internal Trigger 9 (tim_itr9)
B_0x10006:Internal Trigger 10 (tim_itr10)
B_0x10007: Internal trigger 11 (tim_itr11)
B_0x20000: Internal trigger 12 (tim_itr12)
B_0x20001: Internal trigger 13 (tim_itr13)
B_0x20002: Internal trigger 14 (tim_itr14)
B_0x20003: Internal trigger 15 (tim_itr15)

(and repeat that pattern for all other fields that are splitted acrose registers)

Then one can code by just shifting the chosen enum to the TS1 field position.

[hijax_pl]

And this time: ADC_CFGR register and EXTSEL field.

In SVD this single field is split among four 1-bit long ones (according to RM0492) and enumerated values desciptions are messed up (adc_ext_trg0 & adc_ext_trg1 repeated for all 4 "subfields")

RM0492 discusses this as single field, which is correct, i.e.

"Bits 9:5 EXTSEL[4:0]: External trigger selection for regular group

These bits select the external event used to trigger the start of conversion of a regular group:
00000: adc_ext_trg0
00001: adc_ext_trg1
00010: adc_ext_trg2
00011: adc_ext_trg3
00100: adc_ext_trg4
00101: adc_ext_trg5
00110: adc_ext_trg6
00111: adc_ext_trg7
...
11111: adc_ext_trg31"

etc...

Is SVD created from RM or vice versa? Either way I think both RM0492 (page 579) and SVD shall be corrected.