STM32F4 SPI with DMA, LL API: no interruption at the end of the transfer

[FWX]

Hello,
I am using a STM32F427 to read and write data to EEPROM Serial 256-Kb SPI
CAT25256. I use LL API, and DMA full-duplex over SPI. I manage myself the Chip Slect signal.
I can see with logic analyser that datas are sent and received to/from EEPROM correctly.
But I do not have interruption from DMA, neither input or outputstream.
I do not understand why.
The only way to detect the end of the transfer is to look at the BSY flag LL_SPI_IsActiveFlag_BSY(pSPI_Instance). Could-you help me to find where is the problem?
Thank you for help.
Best regards,
                                                        FWX.
I 

[Saket_Om]

Hello @FWX 

Could you enable the transfer complete interrupt on SPI and check if it is set after the data transfer?

[FWX]

Hi Omar,
Transfer complete interrupt is enable for both input and output streams in ddi_eeprom_init():

// Enable Transfer error interrupt
LL_DMA_EnableIT_TE(pDMA_SPI_Instance, InputStreamNumber);
// Enable Transfer complete interrupt
LL_DMA_EnableIT_TC(pDMA_SPI_Instance, InputStreamNumber);
// Enable Direct Mode error interrupt
LL_DMA_EnableIT_DME(pDMA_SPI_Instance, InputStreamNumber);

// Enable Transfer error interrupt
LL_DMA_EnableIT_TE(pDMA_SPI_Instance, OutputStreamNumber);
// Enable Transfer complete interrupt
LL_DMA_EnableIT_TC(pDMA_SPI_Instance, OutputStreamNumber);
// Enable Direct Mode error interrupt
LL_DMA_EnableIT_DME(pDMA_SPI_Instance, OutputStreamNumber);

NVIC is also well confgured in MX_DMA_init():

/* DMA2_Stream3_IRQn interrupt configuration */
NVIC_SetPriority(DMA2_Stream3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),9, 0));
NVIC_EnableIRQ(DMA2_Stream3_IRQn);
/* DMA2_Stream4_IRQn interrupt configuration */
NVIC_SetPriority(DMA2_Stream4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),9, 0));
NVIC_EnableIRQ(DMA2_Stream4_IRQn);

It is why I do not understand why I do not have interrupt.
Thank you for your answer.

                                   FWX.