One way to solve this is to feed back externally the bit clock from SPI/I2S into a timer's pin and use that timer in external clock mode to generate framing using PWM. There may be some sub-TIM-clock-period jitter from mismatch of I2S and TIM clock.
A better way may be to use PLL so that the system clock and I2S clock are set up identically or having an integer mutual ratio, that should remove source of abovementioned jitter. In that case you also might be able to start timer and I2S in a way that they are synchronous, although it's not simple, removing the need to feed back clock externally. As LCE said above, this will probably require a specific frequency crystal, if you are after some particular frequency, although it may quite well be that you don't need some of the "usual audio" frequencies anyway, as you are going to process the signal locally (i.e. don't depend on other equipment into which digital signal is going to be fed, which might require the "usual frequencies").
Yet another, and possibly better, way may be to use SAI set up so that the framing clock output fulfills your requirement, or use two synchronized SAIs, one generating the I2S signal and other generating the framing signal.
A similar method may be to use two I2S clocked from the same PLL tap (if they are available), use one to generate the I2S signal and the other to generate framing alone, with different divider setting.
JW
