How to disable data cache on stm32H743?

SKS2CNC · ‎2024-09-02

I'm using STM32H743 in my project.
If anyone knows how to disable D-cache, please help!
D-cache really interferes with my work - I'm tired of fighting it!
SCB_DisableDCache() - leads to nothing.

mƎALLEm · ‎2024-09-04

Hello,

First, in next time, please use </> button to paste your code. I'm updating your last post.

Second, Table 2 shows the default MPU memory region attributes for Cortex-M. So, this does not mean the cache is enabled by default but the region is cacheable. For example for the regions defined by default as device or strongly ordered and even you enable the cache using SCB_EnableXCache(), that region will not be cacheable.

Third, the difference between what I provided as MPU config is the MPU control mode: MPU privileged default:


  /* Enable the MPU */
  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);

Your code: MPU HFNMI privileged none:


/* Enables the MPU */
LL_MPU_Enable(LL_MPU_CTRL_HFNMI_PRIVDEF_NONE);

So set it to MPU privileged default.

In CubeMx:

You need also to look at the Cortex-M7 programming manual PM0253 STM32F7 Series and STM32H7 Series Cortex®-M7 processor

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View solution in original post

LCE · ‎2024-09-02

Just don't enable it, the source code shouldn't do that on its own.

Don't know about CubeMx, though...

BTW, if CubeMx tells you that you need the cache for any peripheral / middleware to work: that's wrong.

SKS2CNC · ‎2024-09-03

Thank you for your participation. In my projects, I use Cube very sparingly - it often cannot help, but only loads the processor with unnecessary code. Unfortunately, the cache works by default - this is indicated in the documentation and in the debugger. I also observe this when processing arrays - the data does not appear immediately, but with a delay of several milliseconds - in my project this is critical. Flushing the cache by address or shared takes 50 microseconds - too much time and breaks the logic of the state machine. I will accept any advice on how to turn off the cache completely.

mƎALLEm · ‎2024-09-03

You can disable the Cache on a specific memory region using the MPU by configuring it as Shared memory.

Example:


void MPU_Config(void)
{
  MPU_Region_InitTypeDef MPU_InitStruct;
  
  /* Disable the MPU */
  HAL_MPU_Disable();
  /* Configure the MPU attributes as WB-WA for SRAM */
  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
  MPU_InitStruct.BaseAddress = <Your memeory start address>;
  MPU_InitStruct.Size = MPU_REGION_SIZE_<of your memeory region>;
  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
  MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
  MPU_InitStruct.Number = MPU_REGION_NUMBER0;
  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
  MPU_InitStruct.SubRegionDisable = 0x00;
  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;

  HAL_MPU_ConfigRegion(&MPU_InitStruct);

  /* Enable the MPU */
  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}

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SKS2CNC · ‎2024-09-03

Thanks for your help, but could you provide a link to a document describing how to configure the mpu module stm32H743? I would like to understand him better.

mƎALLEm · ‎2024-09-03

Hello,

You can refer to the AN4838 Introduction to memory protection unit management on STM32 MCUs

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Pavel A. · ‎2024-09-03

> Unfortunately, the cache works by default - this is indicated in the documentation and in the debugger.

It would be very surprising if D-cache were enabled "by default" right after MCU startup.

Check this to know if the D-cache is on:


bool dcache_en = !!(SCB->CCR & (uint32_t)SCB_CCR_DC_Msk);

SKS2CNC · ‎2024-09-03

This is exactly what an4839 states - the cache is enabled by default

SKS2CNC · ‎2024-09-03

Unfortunately, your advice leads to HardFault.
At the very beginning when executing the MPU enable instruction.


void MPU_Config(void)
{

/* Disables the MPU */
LL_MPU_Disable();

/** Initializes and configures the Region and the memory to be protected
*/
LL_MPU_ConfigRegion(LL_MPU_REGION_NUMBER0, 0x0, 0x30000000, LL_MPU_REGION_SIZE_128KB|LL_MPU_TEX_LEVEL0|LL_MPU_REGION_FULL_ACCESS|LL_MPU_INSTRUCTION_ACCESS_ENABLE|LL_MPU_ACCESS_SHAREABLE|LL_MPU_ACCESS_NOT_CACHEABLE|LL_MPU_ACCESS_NOT_BUFFERABLE);
LL_MPU_EnableRegion(LL_MPU_REGION_NUMBER0);

/** Initializes and configures the Region and the memory to be protected
*/
LL_MPU_ConfigRegion(LL_MPU_REGION_NUMBER1, 0x0, 0x38000000, LL_MPU_REGION_SIZE_64KB|LL_MPU_TEX_LEVEL0|LL_MPU_REGION_FULL_ACCESS|LL_MPU_INSTRUCTION_ACCESS_ENABLE|LL_MPU_ACCESS_SHAREABLE|LL_MPU_ACCESS_NOT_CACHEABLE|LL_MPU_ACCESS_NOT_BUFFERABLE);
LL_MPU_EnableRegion(LL_MPU_REGION_NUMBER1);
/* Enables the MPU */
LL_MPU_Enable(LL_MPU_CTRL_HFNMI_PRIVDEF_NONE);

}

when executing
LL_MPU_Enable(LL_MPU_CTRL_HFNMI_PRIVDEF_NONE);
follows HardFault.
Any help is welcome!

Pavel A. · ‎2024-09-03

So do you mean by enabling the cache the enable bits in SCB.CCR or default (background of MPU) attributes of internal SRAM? Confused...