U-Boot on STM32H743, Hard Fault..

[Sany]

Hello Guys,

I have a STM32H743IIT6 on a CustomBoard, my Clock is a Quarzoscillator with 25mhz. I have a SDRAM from Winbond with 32 MiB on Bank1, my debug port is USART2, with sdcard for linux later.

I checked out the last release of u-boot from https://github.com/u-boot/u-boot

i tried a lot of days to run the bootloader, with minimal configuration. u-boot has the boards STM32H743-DISCO and STM32H743-EVAL, i tried both with "half" success...

I copied the config form the STM32H743, with C Files, Header and DTS File to my own board, and for the beginning i tried with the internal SRAM from the controller. I changed the HSE Clock to bypass and changed my uart2 pins.

while booting, i become a HardFault.

With google, i found out, R0: 23F36FC0 is out of my DRAM. What do i wrong?

U-Boot 2025.07-rc1-00075-g0c8a89d252c3-dirty (May 04 2025 - 12:02:51 +0200)

Model: STMicroelectronics STM32H743i-EVAL board
DRAM:  Hard fault
pc : 08000a86    lr : 0800bf37    xPSR : 01001800
r12 : 23f36ff8   r3 : 00000000    r2 : fffffffc
r1 : 00000000    r0 : 23f36fc0
Resetting CPU ...

stm32h743-custom_defconfig:

CONFIG_ARM=y
CONFIG_ARCH_STM32=y
CONFIG_SYS_MALLOC_LEN=0x00100000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="st/stm32h743i-custom"
CONFIG_OF_LIBFDT_OVERLAY=y

CONFIG_SYS_LOAD_ADDR=0x24008000
CONFIG_SYS_TEXT_BASE=0x08000000   #internal mcu flash
CONFIG_TEXT_BASE=0x08000000

CONFIG_SYS_SDRAM_BASE=0x24000000  #dram_1
CONFIG_SYS_SDRAM_SIZE=0x00080000

CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SKIP_RELOCATE_UBOOT=y
CONFIG_NR_DRAM_BANKS=1

CONFIG_SYS_DRAM_TEST=y
CONFIG_SYS_DRAM_TEST_LEN=0x00010000

CONFIG_STM32H7=y
CONFIG_TARGET_STM32H743_EVAL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_DEFAULT_FDT_FILE="stm32h743i-custom"
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set

stm32h743-custom.c:

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
 */

#include <dm.h>
#include <init.h>
#include <log.h>
#include <asm/global_data.h>

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	struct udevice *dev;
	int ret;

	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
	if (ret) {
		debug("DRAM init failed: %d\n", ret);
		return ret;
	}

	if (fdtdec_setup_mem_size_base() != 0)
		ret = -EINVAL;

	return ret;
}

int dram_init_banksize(void)
{
	fdtdec_setup_memory_banksize();

	return 0;
}

int board_init(void)
{
	return 0;
}

stm32h743-custom.h:

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <config.h>
#include <linux/sizes.h>

#define CFG_SYS_BOOTMAPSZ		SZ_128K
#define CFG_SYS_FLASH_BASE		0x08000000

#define CFG_SYS_HZ_CLOCK		1000000

#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0)

#include <config_distro_bootcmd.h>
#define CFG_EXTRA_ENV_SETTINGS				\
			"kernel_addr_r=0xD0008000\0"		\
			"fdtfile=stm32h743i-eval.dtb\0"	\
			"fdt_addr_r=0xD0408000\0"		\
			"scriptaddr=0xD0418000\0"		\
			"pxefile_addr_r=0xD0428000\0" \
			"ramdisk_addr_r=0xD0438000\0"		\
			BOOTENV

#endif /* __CONFIG_H */

stm32h743-custom.dts:

/dts-v1/;
#include "stm32h743.dtsi"
#include "stm32h7-pinctrl.dtsi"

/ {
	model = "STMicroelectronics STM32H743i-EVAL board";
	compatible = "st,stm32h743i-eval", "st,stm32h743";

	chosen {
		bootargs = "root=/dev/ram";
		stdout-path = "serial0:115200n8";
	};

	/* AXI‑SRAM (512 KB) */
	memory {
		device_type = "memory";
		reg = <0x24000000 0x00080000>;
		status = "okay";
	};

	aliases {
		serial0 = &usart2;
	};
};


&clk_hse {
	clock-frequency = <25000000>;
	st,bypass;
};


&rtc {
	status = "okay";
};

&mac {
	status = "disabled";
	pinctrl-0 = <&ethernet_rmii>;
	pinctrl-names = "default";
	phy-mode = "rmii";
	phy-handle = <&phy0>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&sdmmc1 {
	pinctrl-names = "default", "opendrain", "sleep";
	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
	pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
	broken-cd;
	st,sig-dir;
	st,neg-edge;
	st,use-ckin;
	bus-width = <4>;
	status = "okay";
};

&usart2 {
	pinctrl-0 = <&usart2_tx_pin &usart2_rx_pin>;
	pinctrl-names = "default";
	status = "okay";
};

&pinctrl {
	usart2_tx_pin: usart2-tx {
		pins {
			pinmux = <STM32_PINMUX('A', 2, AF7)>; /* USART2_TX PA2 */
			bias-disable;
			drive-push-pull;
			slew-rate = <3>;
		};
	};

	usart2_rx_pin: usart2-rx {
		pins {
			pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX PD6 */
			bias-disable;
		};
	};
};