The STM32H743 datasheet section 3.3.2 states that the TCM memories are zero wait state, implying that they run at the core speed of up to 480MHz. It does not make any claim about the rest of the SRAM. Figure 2 in the datasheet shows all the AXI and AHB buses running at 240MHz.
The reference manual RM0433 figure 49 also shows the AXI and AHBs in domains 1 and 2 running at up to 240MHz.
However the reference manual section 2.4 says that AHB SRAM and AXI SRAM “can be addressed at maximum system clock frequency without wait state.”
Is this correct? How can the bus and matrix be clocked at half the core speed and never introduce wait states?
Table 33 of the datsheet also states that running from SRAM1 with the cache disabled, the performance is less than a quarter of running from ITCM (it doesn’t say where the data is for the benchmark, but for a fair comparison it would need to have been in the DTCM).
