DFU issue with system Boatloader: ''Matching Not good''..

rumlyen · ‎2017-04-12

Posted on April 12, 2017 at 17:43

Hi,

I'm using STM32L476RE in a custom board without HSE. I ported Discovery (76VG) Blink Project (following Clive1's DFU system bootloader) and successfully tested on my board in both Keil and TureStudio. It’s only a 4KB .DFU file to load by DfuseDemo. Now, in my real Truestudio project generated by CubeMx, the .dfu file is 68KB and DFU showing following error ''Matching is not good'' (attached).

Am I doing something wrong in configuration? I can’t use Keil here as code size exceeds limit. Datasheet says, System memory 28KB aliased on 0x00000000-0x000FFFF and SRAM1 96KB and Flash 1MB (Attached Image). I request your guidance to solve this issue. In the final version of my custom board, I'll only have USB (or SD) to load program.

In Keil, I've changed my startup_stm32l476xx.s file

Reboot_Loader PROC

EXPORT Reboot_Loader

LDR R0, =0x40021060 ;// RCC_APB2ENR Address 0x40021000 (Base)+60 (offset)

LDR R1, =0x00000001 ;// ENABLE SYSCFG CLOCK

STR R1, [R0, #0]

LDR R0, =0x40010000 ;// SYSCFG_MEMRMP

LDR R1, =0x00000001 ;// MAP ROM AT ZERO

STR R1, [R0, #0]

LDR R0, =0x1FFF0000 ;// ROM BASE of L4

LDR SP,[R0, #0] ;// SP @ +0

LDR R0,[R0, #4] ;// PC @ +4

BX R0

ENDP ;

Reset_Handler PROC

EXPORT Reset_Handler [WEAK]

IMPORT SystemInit

IMPORT __main

LDR R0, =0x20017FF0 ; // End Address of SRAM1 (STM32L4) 0x20017FFF --Bootloader_Ram_Key_Address

LDR R1, =0xDEADBEEF ;// Bootloader_Key_Value

LDR R2, [R0, #0]

STR R0, [R0, #0] ;// Invalidate Bootloader_Key_Value

CMP R2, R1

BEQ Reboot_Loader ; /* End bootloader jumping */

LDR R0, =SystemInit

BLX R0

LDR R0, =__main

BX R0

ENDP

; Reset handler

In Atollic Truestudio,

.section .text.Reboot_Handler

.type Reboot_Handler, %function

Reboot_Handler:

LDR R0, =0x40021060 // RCC_APB2ENR Address 0x40021000 (Base)+60 (offset)

LDR R1, =0x00000001 // ENABLE SYSCFG CLOCK

STR R1, [R0, #0]

LDR R0, =0x40010000 // SYSCFG_MEMRMP

LDR R1, =0x00000001 // MAP ROM AT ZERO

STR R1, [R0, #0]

LDR R0, =0x1FFF0000 // ROM BASE of L4

LDR SP,[R0, #0] // SP @ +0

LDR R0,[R0, #4] // PC @ +4

BX R0

.size Reboot_Handler, .-Reboot_Handler

.section .text.Reset_Handler

.weak Reset_Handler

.type Reset_Handler, %function

Reset_Handler:

LDR R0, =0x20017FF0 // End Address of SRAM1 (STM32L4) 0x20017FFF --Bootloader_Ram_Key_Address

LDR R1, =0xDEADBEEF // Bootloader_Key_Value

LDR R2, [R0, #0]

STR R0, [R0, #0] // Invalidate Bootloader_Key_Value

CMP R2, R1

BEQ Reboot_Handler // Jump to DfuModeEntry Lable if Bootloader_Key_Value matches

// Conitnue without entering DFU Mode

ldr sp, =_estack /* Atollic update: set stack pointer */

/*Copy the data segment initializers from flash to SRAM */

movs r1, #0

b LoopCopyDataInit

CopyDataInit:

ldr r3, =_sidata

ldr r3, [r3, r1]

str r3, [r0, r1]

adds r1, r1, #4

LoopCopyDataInit:

ldr r0, =_sdata

ldr r3, =_edata

adds r2, r0, r1

cmp r2, r3

bcc CopyDataInit

ldr r2, =_sbss

b LoopFillZerobss

/* Zero fill the bss segment. */

FillZerobss:

movs r3, #0

str r3, [r2], #4

LoopFillZerobss:

ldr r3, = _ebss

cmp r2, r3

bcc FillZerobss

/* Call the clock system intitialization function.*/

bl SystemInit

/* Call static constructors */

bl __libc_init_array

/* Call the application's entry point.*/

bl main

LoopForever:

b LoopForever

.size Reset_Handler, .-Reset_Handler

#stm32l476 #dfu

Note: this post was migrated and contained many threaded conversations, some content may be missing.

Tesla DeLorean · ‎2017-04-12

Posted on April 12, 2017 at 18:14

The other 64K+ seemed to go Ok.

One reported anomaly is that the System Loader expects 8-byte aligned/sized writes. The .HEX might have voids where this doesn't happen.

The tool I wrote should handle that, if not we can dig a bit deeper into your specific issue here.

https://community.st.com/0D70X000006SYHeSAO

I don't have any

STM32L476RE parts to evaluate this myself.

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View solution in original post

Tesla DeLorean · ‎2017-04-12

Posted on April 12, 2017 at 18:14

The other 64K+ seemed to go Ok.

One reported anomaly is that the System Loader expects 8-byte aligned/sized writes. The .HEX might have voids where this doesn't happen.

The tool I wrote should handle that, if not we can dig a bit deeper into your specific issue here.

https://community.st.com/0D70X000006SYHeSAO

I don't have any

STM32L476RE parts to evaluate this myself.

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

rumlyen · ‎2017-04-12

Posted on April 12, 2017 at 20:55

Thank you, It worked immediately.. Good to have whole thing in a post.

It took quite a long for me to edit True Studio project to fit your bootloader. I guess L476 users will be benefited from it.

I appreciate your time

Jack Phan · ‎2017-09-28

Posted on September 28, 2017 at 20:39

Hi Lyen,

I have the same problem, could you please share your latest code to work in this case. (code of

Reboot_Handler).

Thanks,

Tesla DeLorean · ‎2017-09-28

Posted on September 28, 2017 at 21:07

It represents code/concepts I had presented. The general solution would be to set the boot rom base to be zero, but I think the L4x6 devices all have it situated at 0x1FFF0000

What exactly is *your* issue, and what part are *you* using?

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Jack Phan · ‎2017-09-28

Posted on September 28, 2017 at 21:55

Hi Clive One,

Thanks for your quick response.

My device is STM32L476JEY (BGA footprint). I try to update firmware through USB. I had the USB communication working well. So I will use a command through USB to set the device to boot mode for updating a new firmware.

For testing, now I set to bootmode after 10 seconds when power On.

In the file startup_stm32l476xx.s, I modified as follows but it doesn't work.

// ===

.section .text.Reboot_Handler

.type Reboot_Handler, %function

Reboot_Handler:

LDR R0, =0x40021060 // RCC_APB2ENR Address 0x40021000 (Base)+60 (offset)

LDR R1, =0x00000001 // ENABLE SYSCFG CLOCK

STR R1, [R0, &sharp0]

LDR R0, =0x40010000 // SYSCFG_MEMRMP

LDR R1, =0x00000001 // MAP ROM AT ZERO

STR R1, [R0, &sharp0]

LDR R0, =0x1FFF0000 // ROM BASE of L4

LDR SP,[R0, &sharp0] // SP @ +0

LDR R0,[R0, &sharp4] // PC @ +4

BX R0

.size Reboot_Handler, .-Reboot_Handler

.section .text.Reset_Handler

.weak Reset_Handler

.type Reset_Handler, %function

Reset_Handler:

ldr r0, =0x20018000

ldr r1, =0xDEADBEEF

ldr r2, [r0, &sharp0]

str r0, [r0, &sharp0]

cmp r2, r1

beq Reboot_Handler

ldr sp, =_estack /* Atollic update: set stack pointer */

/* Copy the data segment initializers from flash to SRAM */

movs r1, &sharp0

b LoopCopyDataInit

...

// === after 10 seconds

static void osTimerPeriodCallback(void const *argument)

{

(void) argument;

HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_7);

if ( CounterTestBootloader > 80) {

JmpToBootloader();

}

CounterTestBootloader++;

}

// ===

&sharpdefine RAM_BOOT_LOADER_SIGNATURE_VALUE 0xDEADBEEF

&sharpdefine RAM_BOOT_LOADER_SIGNATURE_ADDRESS 0x20018000

void JmpToBootloader(void) {

*((unsigned long *)RAM_BOOT_LOADER_SIGNATURE_ADDRESS) = RAM_BOOT_LOADER_SIGNATURE_VALUE;

NVIC_SystemReset();

}

Jack Phan · ‎2017-09-28

Posted on September 28, 2017 at 21:58

I see error that, it couldn't go to normal work because of line: ldr r2, [r0, &sharp0], and then I modified as follows but it's still not going to DFU mode.

// ===

.section .text.Reset_Handler

.weak Reset_Handler

.type Reset_Handler, %function

Reset_Handler:

//ldr r0, =0x20018000

//ldr r1, =0xDEADBEEF

//ldr r2, [r0, &sharp0]

//str r0, [r0, &sharp0]

//cmp r2, r1

//beq Reboot_Handler

ldr r0, =0x20018000

ldr r3, =0xDEADBEEF

adds r2, r0, r1

cmp r2, r3

beq Reboot_Handler

// Conitnue without entering DFU Mode

ldr sp, =_estack /* Atollic update: set stack pointer */

...

// ===

Tesla DeLorean · ‎2017-09-28

Posted on September 28, 2017 at 22:59

ldr r0, =0x20018000 ; Isn't this beyond the end of SRAM1? Going to Hard Fault

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Jack Phan · ‎2017-09-28

Posted on September 28, 2017 at 23:04

In the file STM32L476JEYx_FLASH.ld, it has

/* Entry Point */

ENTRY(Reset_Handler)

/* Highest address of the user mode stack */

_estack = 0x20018000; /* end of RAM */

/* Generate a link error if heap and stack don't fit into RAM */

_Min_Heap_Size = 0x200; /* required amount of heap */

_Min_Stack_Size = 0x400; /* required amount of stack */

So I think it's OK?

Jack Phan · ‎2017-09-28

Posted on September 28, 2017 at 23:06

more detail:

/* Entry Point */

ENTRY(Reset_Handler)

/* Highest address of the user mode stack */

_estack = 0x20018000; /* end of RAM */

/* Generate a link error if heap and stack don't fit into RAM */

_Min_Heap_Size = 0x200; /* required amount of heap */

_Min_Stack_Size = 0x400; /* required amount of stack */

/* Specify the memory areas */

MEMORY

{

RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K

RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 32K

FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K

}